[src/trunk]: src/sys/arch/aarch64/aarch64 Always issue isb after cpacr_el1 wr...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/562a48f2f728
branches:  trunk
changeset: 948307:562a48f2f728
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sat Dec 26 00:55:26 2020 +0000

description:
Always issue isb after cpacr_el1 writes since it is a context-changing
operation.

diffstat:

 sys/arch/aarch64/aarch64/cpuswitch.S  |  7 +++++--
 sys/arch/aarch64/aarch64/locore.S     |  5 +++--
 sys/arch/aarch64/aarch64/locore_el2.S |  5 +++--
 3 files changed, 11 insertions(+), 6 deletions(-)

diffs (94 lines):

diff -r 5ed62325ba21 -r 562a48f2f728 sys/arch/aarch64/aarch64/cpuswitch.S
--- a/sys/arch/aarch64/aarch64/cpuswitch.S      Sat Dec 26 00:16:16 2020 +0000
+++ b/sys/arch/aarch64/aarch64/cpuswitch.S      Sat Dec 26 00:55:26 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.31 2020/10/22 07:36:02 skrll Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.32 2020/12/26 00:55:26 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -38,7 +38,7 @@
 #include "opt_ddb.h"
 #include "opt_kasan.h"
 
-RCSID("$NetBSD: cpuswitch.S,v 1.31 2020/10/22 07:36:02 skrll Exp $")
+RCSID("$NetBSD: cpuswitch.S,v 1.32 2020/12/26 00:55:26 jmcneill Exp $")
 
        ARMV8_DEFINE_OPTIONS
 
@@ -86,6 +86,7 @@
        DISABLE_INTERRUPT
        mov     sp, x4                  /* restore stack pointer */
        msr     cpacr_el1, x5           /* restore cpacr_el1 */
+       isb
 
 #ifdef ARMV83_PAC
        /* Switch the PAC key. */
@@ -191,6 +192,7 @@
 
        mov     x5, #CPACR_FPEN_NONE
        msr     cpacr_el1, x5           /* cpacr_el1 = CPACR_FPEN_NONE */
+       isb
 
 #ifdef ARMV83_PAC
        /* Switch the PAC key. */
@@ -223,6 +225,7 @@
 
        mov     sp, x4                  /* restore pinned_lwp sp */
        msr     cpacr_el1, x5           /* restore pinned_lwp cpacr */
+       isb
 
 #ifdef ARMV83_PAC
        /* Restore the PAC key. */
diff -r 5ed62325ba21 -r 562a48f2f728 sys/arch/aarch64/aarch64/locore.S
--- a/sys/arch/aarch64/aarch64/locore.S Sat Dec 26 00:16:16 2020 +0000
+++ b/sys/arch/aarch64/aarch64/locore.S Sat Dec 26 00:55:26 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.74 2020/10/22 07:16:06 ryo Exp $  */
+/*     $NetBSD: locore.S,v 1.75 2020/12/26 00:55:26 jmcneill Exp $     */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -38,7 +38,7 @@
 #include <aarch64/hypervisor.h>
 #include "assym.h"
 
-RCSID("$NetBSD: locore.S,v 1.74 2020/10/22 07:16:06 ryo Exp $")
+RCSID("$NetBSD: locore.S,v 1.75 2020/12/26 00:55:26 jmcneill Exp $")
 
 #ifdef AARCH64_DEVICE_MEM_STRONGLY_ORDERED
 #define        MAIR_DEVICE_MEM         MAIR_DEVICE_nGnRnE
@@ -250,6 +250,7 @@
 
        /* No trap system register access, and Trap FP/SIMD access */
        msr     cpacr_el1, xzr
+       isb
 
        /* allow to read CNTVCT_EL0 and CNTFRQ_EL0 from EL0 */
        mrs     x0, cntkctl_el1
diff -r 5ed62325ba21 -r 562a48f2f728 sys/arch/aarch64/aarch64/locore_el2.S
--- a/sys/arch/aarch64/aarch64/locore_el2.S     Sat Dec 26 00:16:16 2020 +0000
+++ b/sys/arch/aarch64/aarch64/locore_el2.S     Sat Dec 26 00:55:26 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore_el2.S,v 1.7 2020/09/15 09:28:20 ryo Exp $       */
+/*     $NetBSD: locore_el2.S,v 1.8 2020/12/26 00:55:26 jmcneill Exp $  */
 
 /*-
  * Copyright (c) 2012-2014 Andrew Turner
@@ -32,7 +32,7 @@
 #include <aarch64/hypervisor.h>
 #include "assym.h"
 
-RCSID("$NetBSD: locore_el2.S,v 1.7 2020/09/15 09:28:20 ryo Exp $")
+RCSID("$NetBSD: locore_el2.S,v 1.8 2020/12/26 00:55:26 jmcneill Exp $")
 
 /*
  * For use in #include "locore_el2.S".
@@ -85,6 +85,7 @@
        bic     x2, x2, #CPACR_FPEN
        orr     x2, x2, #CPACR_FPEN_ALL
        msr     cpacr_el1, x2
+       isb
 
        /* Don't trap to EL2 on access to various registers. */
        mov     x2, #CPTR_RES1