[src/trunk]: src/sys/arch/arm/cortex Disable 1ofN distribution of SPIs by def...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/ea2b8c7dc393
branches:  trunk
changeset: 954051:ea2b8c7dc393
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun Mar 28 11:13:24 2021 +0000

description:
Disable 1ofN distribution of SPIs by default. This is a workaround for an
issue in the USB stack -- signaling transfer complete on multiple PEs can
cause transfer completions to be processed out of order.

diffstat:

 sys/arch/arm/cortex/gicv3.c |  15 +++++++++++----
 1 files changed, 11 insertions(+), 4 deletions(-)

diffs (50 lines):

diff -r ea906d922575 -r ea2b8c7dc393 sys/arch/arm/cortex/gicv3.c
--- a/sys/arch/arm/cortex/gicv3.c       Sun Mar 28 11:08:01 2021 +0000
+++ b/sys/arch/arm/cortex/gicv3.c       Sun Mar 28 11:13:24 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.43 2021/02/23 10:03:04 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.44 2021/03/28 11:13:24 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -31,7 +31,7 @@
 #define        _INTR_PRIVATE
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.43 2021/02/23 10:03:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.44 2021/03/28 11:13:24 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/kernel.h>
@@ -65,6 +65,13 @@
 #define        GIC_PRIO_SHIFT_NS               4
 #define        GIC_PRIO_SHIFT_S                3
 
+/*
+ * Set to true if you want to use 1 of N interrupt distribution for SPIs
+ * when available. Disabled by default because it causes issues with the
+ * USB stack.
+ */
+bool gicv3_use_1ofn = false;
+
 static struct gicv3_softc *gicv3_softc;
 
 static inline uint32_t
@@ -195,7 +202,7 @@
                 * If 1 of N SPI routing is supported, route MP-safe interrupts to all
                 * participating PEs. Otherwise, just route to the primary PE.
                 */
-               if (is->is_mpsafe && GIC_SUPPORTS_1OFN(sc)) {
+               if (is->is_mpsafe && GIC_SUPPORTS_1OFN(sc) && gicv3_use_1ofn) {
                        irouter = GICD_IROUTER_Interrupt_Routing_mode;
                } else {
                        irouter = sc->sc_irouter[0];
@@ -498,7 +505,7 @@
        const int set = kcpuset_countset(affinity);
        if (set == 1) {
                irouter = sc->sc_irouter[kcpuset_ffs(affinity) - 1];
-       } else if (set == ncpu && GIC_SUPPORTS_1OFN(sc)) {
+       } else if (set == ncpu && GIC_SUPPORTS_1OFN(sc) && gicv3_use_1ofn) {
                irouter = GICD_IROUTER_Interrupt_Routing_mode;
        } else {
                return EINVAL;