[src/trunk]: src/sys/arch/sparc64/sparc64 sun4v: handle spill trap properly w...

[palle <palle%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/750d0e7de0a1
branches:  trunk
changeset: 954170:750d0e7de0a1
user:      palle <palle%NetBSD.org@localhost>
date:      Tue Mar 30 20:03:14 2021 +0000

description:
sun4v: handle spill trap properly when trap level is 1 and otherwin is non-zero - ensure that all windows are spilled to the pcb like the sun4u winfixsave code path

diffstat:

 sys/arch/sparc64/sparc64/locore.s |  75 +++++++++++++++++++++++++++++++++++++-
 1 files changed, 73 insertions(+), 2 deletions(-)

diffs (96 lines):

diff -r 33e3f114d811 -r 750d0e7de0a1 sys/arch/sparc64/sparc64/locore.s
--- a/sys/arch/sparc64/sparc64/locore.s Tue Mar 30 19:45:04 2021 +0000
+++ b/sys/arch/sparc64/sparc64/locore.s Tue Mar 30 20:03:14 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.s,v 1.425 2021/02/22 09:56:42 palle Exp $       */
+/*     $NetBSD: locore.s,v 1.426 2021/03/30 20:03:14 palle Exp $       */
 
 /*
  * Copyright (c) 2006-2010 Matthew R. Green
@@ -234,7 +234,7 @@
        .endm
 
        .macro sun4v_tl1_uspill_other
-       ba,a,pt %xcc, pcbspill_others
+       ba,a,pt %xcc, pcbspill_other
         nop
        .align 128
        .endm
@@ -3485,6 +3485,77 @@
        Debugger()
        NOTREACHED
 
+
+pcbspill_other:
+       
+       set     CPUINFO_VA, %g6
+       ldx     [%g6 + CI_CPCB], %g6
+       
+       GET_CTXBUSY %g1
+
+       ldx     [%g1], %g1                              ! kernel pmap is ctx 0
+       
+       srlx    %g6, STSHIFT, %g7
+       and     %g7, STMASK, %g7
+       sll     %g7, 3, %g7                             ! byte offset into ctxbusy
+       add     %g7, %g1, %g1
+       ldxa    [%g1] ASI_PHYS_CACHED, %g1              ! Load pointer to directory
+
+       srlx    %g6, PDSHIFT, %g7                       ! Do page directory
+       and     %g7, PDMASK, %g7
+       sll     %g7, 3, %g7
+       brz,pn  %g1, pcbspill_other_fail
+        add    %g7, %g1, %g1
+       ldxa    [%g1] ASI_PHYS_CACHED, %g1
+       srlx    %g6, PTSHIFT, %g7                       ! Convert to ptab offset
+       and     %g7, PTMASK, %g7
+       brz     %g1, pcbspill_other_fail
+        sll    %g7, 3, %g7
+       add     %g1, %g7, %g7
+       ldxa    [%g7] ASI_PHYS_CACHED, %g7              ! This one is not
+       brgez   %g7, pcbspill_other_fail
+        srlx   %g7, PGSHIFT, %g7                       ! Isolate PA part
+       sll     %g6, 32-PGSHIFT, %g6                    ! And offset
+       sllx    %g7, PGSHIFT+8, %g7                     ! There are 8 bits to the left of the PA in the TTE
+       srl     %g6, 32-PGSHIFT, %g6
+       srax    %g7, 8, %g7
+       or      %g7, %g6, %g6                           ! Then combine them to form PA
+
+       wr      %g0, ASI_PHYS_CACHED, %asi              ! Use ASI_PHYS_CACHED to prevent possible page faults
+
+       lduba   [%g6 + PCB_NSAVED] %asi, %g7            ! Fetch current nsaved from the pcb
+       sllx    %g7, 7, %g5                             ! 8+8 registers each 8 bytes = 128 bytes (2^7)
+       add     %g6, %g5, %g5                           ! Offset into pcb_rw
+1:     
+       SPILL   stxa, %g5 + PCB_RW, 8, %asi             ! Store the locals and ins
+
+       add     %g5, 16*8, %g5                          ! Next location for saved register windows
+
+       stxa    %o6, [%g5 + PCB_RW + (14*8)] %asi       ! Save %sp so we can write these all out
+       
+       saved                                           ! Increments %cansave and decrements %otherwin
+       
+       rdpr    %cwp, %g1                               ! shift register window forward
+       inc     %g1
+       wrpr    %g1, %cwp
+
+
+       inc     %g7                                     ! increment number of saved register windows
+
+       rdpr    %otherwin, %g1                          ! Check to see if done spill'ing otherwin
+       brnz,pt %g1, 1b
+        nop
+       
+       stba    %g7, [%g6 + PCB_NSAVED] %asi
+
+       retry
+       NOTREACHED
+
+pcbspill_other_fail:
+       Debugger()
+       NOTREACHED
+
+
 spill_normal_to_user_stack:
        mov     %sp, %g6                                                ! calculate virtual address of destination stack
        add     %g6, BIAS, %g6