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[src/trunk]: src/sys/dev/pci Regen.
details: https://anonhg.NetBSD.org/src/rev/1794167836fd
branches: trunk
changeset: 957147:1794167836fd
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Fri Nov 20 01:29:46 2020 +0000
description:
Regen.
diffstat:
sys/dev/pci/pcidevs.h | 219 +-
sys/dev/pci/pcidevs_data.h | 14399 ++++++++++++++++++++++--------------------
2 files changed, 7641 insertions(+), 6977 deletions(-)
diffs (truncated from 19591 to 300 lines):
diff -r dec755563d79 -r 1794167836fd sys/dev/pci/pcidevs.h
--- a/sys/dev/pci/pcidevs.h Fri Nov 20 01:29:12 2020 +0000
+++ b/sys/dev/pci/pcidevs.h Fri Nov 20 01:29:46 2020 +0000
@@ -1,10 +1,10 @@
-/* $NetBSD: pcidevs.h,v 1.1407 2020/11/19 22:03:16 reinoud Exp $ */
+/* $NetBSD: pcidevs.h,v 1.1408 2020/11/20 01:29:46 msaitoh Exp $ */
/*
* THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD: pcidevs,v 1.1420 2020/11/19 21:59:07 reinoud Exp
+ * NetBSD: pcidevs,v 1.1421 2020/11/20 01:29:12 msaitoh Exp
*/
/*
@@ -3146,9 +3146,59 @@
#define PCI_PRODUCT_INTEL_IVYBRIDGE_IGD_1 0x0162 /* Ivy Bridge Integrated Graphics Device */
#define PCI_PRODUCT_INTEL_IVYBRIDGE_M_IGD_1 0x0166 /* Ivy Bridge Integrated Graphics Device */
#define PCI_PRODUCT_INTEL_IVYBRIDGE_S_IGD_1 0x016a /* Ivy Bridge Integrated Graphics Device */
-#define PCI_PRODUCT_INTEL_CMTLK_U_LPC 0x0284 /* Comet Lake U LPC or eSPI */
+#define PCI_PRODUCT_INTEL_CMTLK_U_P_LPC 0x0284 /* Comet Lake U (Premium) LPC or eSPI */
+#define PCI_PRODUCT_INTEL_CMTLK_U_LPC 0x0285 /* Comet Lake U LPC or eSPI */
+#define PCI_PRODUCT_INTEL_CMTLK_P2SB 0x02a0 /* Comet Lake P2SB */
+#define PCI_PRODUCT_INTEL_CMTLK_PMC 0x02a1 /* Comet Lake PMC */
#define PCI_PRODUCT_INTEL_CMTLK_SMB 0x02a3 /* Comet Lake SMBus */
#define PCI_PRODUCT_INTEL_CMTLK_SPI 0x02a4 /* Comet Lake SPI (FLASH) */
+#define PCI_PRODUCT_INTEL_CMTLK_TRACE 0x02a6 /* Comet Lake Trace Hub */
+#define PCI_PRODUCT_INTEL_CMTLK_UART_0 0x02a8 /* Comet Lake UART 0 */
+#define PCI_PRODUCT_INTEL_CMTLK_UART_1 0x02a9 /* Comet Lake UART 1 */
+#define PCI_PRODUCT_INTEL_CMTLK_SPI_0 0x02aa /* Comet Lake SPI 0 */
+#define PCI_PRODUCT_INTEL_CMTLK_SPI_1 0x02ab /* Comet Lake SPI 1 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_9 0x02b0 /* Comet Lake PCIe Root Port 9 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_10 0x02b1 /* Comet Lake PCIe Root Port 10 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_11 0x02b2 /* Comet Lake PCIe Root Port 11 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_12 0x02b3 /* Comet Lake PCIe Root Port 12 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_13 0x02b4 /* Comet Lake PCIe Root Port 13 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_14 0x02b5 /* Comet Lake PCIe Root Port 14 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_15 0x02b6 /* Comet Lake PCIe Root Port 15 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_16 0x02b7 /* Comet Lake PCIe Root Port 16 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_1 0x02b8 /* Comet Lake PCIe Root Port 1 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_2 0x02b9 /* Comet Lake PCIe Root Port 2 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_3 0x02ba /* Comet Lake PCIe Root Port 3 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_4 0x02bb /* Comet Lake PCIe Root Port 4 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_5 0x02bc /* Comet Lake PCIe Root Port 5 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_6 0x02bd /* Comet Lake PCIe Root Port 6 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_7 0x02be /* Comet Lake PCIe Root Port 7 */
+#define PCI_PRODUCT_INTEL_CMTLK_PCIE_8 0x02bf /* Comet Lake PCIe Root Port 8 */
+#define PCI_PRODUCT_INTEL_CMTLK_EMMC 0x02c4 /* Comet Lake eMMC */
+#define PCI_PRODUCT_INTEL_CMTLK_I2C_4 0x02c5 /* Comet Lake I2C 4 */
+#define PCI_PRODUCT_INTEL_CMTLK_I2C_5 0x02c6 /* Comet Lake I2C 5 */
+#define PCI_PRODUCT_INTEL_CMTLK_UART_2 0x02c7 /* Comet Lake UART 2 */
+#define PCI_PRODUCT_INTEL_CMTLK_HDA 0x02c8 /* Comet Lake HD Audio */
+#define PCI_PRODUCT_INTEL_CMTLK_AHCI 0x02d3 /* Comet Lake SATA (AHCI) */
+#define PCI_PRODUCT_INTEL_CMTLK_RAID 0x02d5 /* Comet Lake SATA (RAID) */
+#define PCI_PRODUCT_INTEL_CMTLK_RAID_P 0x02d7 /* Comet Lake SATA (RAID) premium */
+#define PCI_PRODUCT_INTEL_CMTLK_MEI_1 0x02e0 /* Comet Lake MEI 1 */
+#define PCI_PRODUCT_INTEL_CMTLK_MEI_2 0x02e1 /* Comet Lake MEI 2 */
+#define PCI_PRODUCT_INTEL_CMTLK_IDER 0x02e2 /* Comet Lake IDE-R */
+#define PCI_PRODUCT_INTEL_CMTLK_KT 0x02e3 /* Comet Lake KT */
+#define PCI_PRODUCT_INTEL_CMTLK_MEI_3 0x02e4 /* Comet Lake MEI 3 */
+#define PCI_PRODUCT_INTEL_CMTLK_MEI_4 0x02e5 /* Comet Lake MEI 4 */
+#define PCI_PRODUCT_INTEL_CMTLK_I2C_0 0x02e8 /* Comet Lake I2C 0 */
+#define PCI_PRODUCT_INTEL_CMTLK_I2C_1 0x02e9 /* Comet Lake I2C 1 */
+#define PCI_PRODUCT_INTEL_CMTLK_I2C_2 0x02ea /* Comet Lake I2C 2 */
+#define PCI_PRODUCT_INTEL_CMTLK_I2C_3 0x02eb /* Comet Lake I2C 3 */
+#define PCI_PRODUCT_INTEL_CMTLK_XHCI 0x02ed /* Comet Lake USB 3.2 Gen 2x1 xHCI */
+#define PCI_PRODUCT_INTEL_CMTLK_XDCI 0x02ee /* Comet Lake USB 3.2 Gen 1x1 xDCI */
+#define PCI_PRODUCT_INTEL_CMTLK_SSRAM 0x02ef /* Comet Lake Shared SRAM */
+#define PCI_PRODUCT_INTEL_CMTLK_CNVI_WIFI 0x02f0 /* Comet Lake CNVi WiFi */
+#define PCI_PRODUCT_INTEL_CMTLK_SDXC 0x02f5 /* Comet Lake SDXC */
+#define PCI_PRODUCT_INTEL_CMTLK_THERM 0x02f9 /* Comet Lake Thermal */
+#define PCI_PRODUCT_INTEL_CMTLK_SPI_2 0x02fb /* Comet Lake SPI 2 */
+#define PCI_PRODUCT_INTEL_CMTLK_ISH 0x02fc /* Comet Lake Integrated Sensor Hub */
#define PCI_PRODUCT_INTEL_CMTLK_PCIE_9 0x02b0 /* Comet Lake PCIe Root Port 9 */
#define PCI_PRODUCT_INTEL_CMTLK_PCIE_10 0x02b1 /* Comet Lake PCIe Root Port 10 */
#define PCI_PRODUCT_INTEL_CMTLK_PCIE_11 0x02b2 /* Comet Lake PCIe Root Port 11 */
@@ -3214,6 +3264,70 @@
#define PCI_PRODUCT_INTEL_PCMC 0x04a3 /* 82434LX/NX PCI, Cache and Memory Controller (PCMC) */
#define PCI_PRODUCT_INTEL_GDT_RAID1 0x0600 /* GDT RAID */
#define PCI_PRODUCT_INTEL_GDT_RAID2 0x061f /* GDT RAID */
+#define PCI_PRODUCT_INTEL_4HS_LPC_H470 0x0684 /* H470 LPC */
+#define PCI_PRODUCT_INTEL_4HS_LPC_Z490 0x0685 /* Z490 LPC */
+#define PCI_PRODUCT_INTEL_4HS_LPC_Q470 0x0687 /* Q470 LPC */
+#define PCI_PRODUCT_INTEL_4HS_LPC_QM480 0x068c /* QM480 LPC */
+#define PCI_PRODUCT_INTEL_4HS_LPC_HM470 0x068d /* HM470 LPC */
+#define PCI_PRODUCT_INTEL_4HS_LPC_WM490 0x068e /* WM490 LPC */
+#define PCI_PRODUCT_INTEL_4HS_LPC_W480 0x0697 /* W480 LPC */
+#define PCI_PRODUCT_INTEL_4HS_H_P2SB 0x06a0 /* 400 Series P2SB */
+#define PCI_PRODUCT_INTEL_4HS_H_PMC 0x06a1 /* 400 Series PMC */
+#define PCI_PRODUCT_INTEL_4HS_H_SMB 0x06a3 /* 400 Series SMBus */
+#define PCI_PRODUCT_INTEL_4HS_H_SPI_FLASH 0x06a4 /* 400 Series SPI (FLASH) */
+#define PCI_PRODUCT_INTEL_4HS_H_TRACE 0x06a6 /* 400 Series Trace Hub */
+#define PCI_PRODUCT_INTEL_4HS_H_UART_0 0x06a8 /* 400 Series UART 0 */
+#define PCI_PRODUCT_INTEL_4HS_H_UART_1 0x06a9 /* 400 Series UART 1 */
+#define PCI_PRODUCT_INTEL_4HS_H_GSPI_0 0x06aa /* 400 Series GSPI 0 */
+#define PCI_PRODUCT_INTEL_4HS_H_GSPI_1 0x06ab /* 400 Series GSPI 1 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_21 0x06ac /* 400 Series PCIe Root Port 21 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_22 0x06ad /* 400 Series PCIe Root Port 22 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_23 0x06ae /* 400 Series PCIe Root Port 23 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_24 0x06af /* 400 Series PCIe Root Port 24 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_9 0x06b0 /* 400 Series PCIe Root Port 9 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_10 0x06b1 /* 400 Series PCIe Root Port 10 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_11 0x06b2 /* 400 Series PCIe Root Port 11 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_12 0x06b3 /* 400 Series PCIe Root Port 12 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_13 0x06b4 /* 400 Series PCIe Root Port 13 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_14 0x06b5 /* 400 Series PCIe Root Port 14 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_15 0x06b6 /* 400 Series PCIe Root Port 15 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_16 0x06b7 /* 400 Series PCIe Root Port 16 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_1 0x06b8 /* 400 Series PCIe Root Port 1 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_2 0x06b9 /* 400 Series PCIe Root Port 2 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_3 0x06ba /* 400 Series PCIe Root Port 3 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_4 0x06bb /* 400 Series PCIe Root Port 4 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_5 0x06bc /* 400 Series PCIe Root Port 5 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_6 0x06bd /* 400 Series PCIe Root Port 6 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_7 0x06be /* 400 Series PCIe Root Port 7 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_8 0x06bf /* 400 Series PCIe Root Port 8 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_17 0x06c0 /* 400 Series PCIe Root Port 17 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_18 0x06c1 /* 400 Series PCIe Root Port 18 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_19 0x06c2 /* 400 Series PCIe Root Port 19 */
+#define PCI_PRODUCT_INTEL_4HS_H_PCIE_20 0x06c3 /* 400 Series PCIe Root Port 20 */
+#define PCI_PRODUCT_INTEL_4HS_H_UART_2 0x06c7 /* 400 Series UART 2 */
+#define PCI_PRODUCT_INTEL_4HS_H_CAVS 0x06c8 /* 400 Series cAVS 1.8 */
+#define PCI_PRODUCT_INTEL_4HS_H_D_AHCI 0x06d2 /* 400 Series SATA (AHCI) desktop */
+#define PCI_PRODUCT_INTEL_4HS_H_M_AHIC 0x06d3 /* 400 Series SATA (AHCI) mobile */
+#define PCI_PRODUCT_INTEL_4HS_H_M_RAID 0x06d5 /* 400 Series SATA (RAID) mobile */
+#define PCI_PRODUCT_INTEL_4HS_H_M_P_RAID 0x06d7 /* 400 Series SATA (RAID) premium mobile */
+#define PCI_PRODUCT_INTEL_4HS_H_AHCI_OPTANE 0x06de /* 400 Series SATA (AHCI) Optane */
+#define PCI_PRODUCT_INTEL_4HS_H_HECI_1 0x06e0 /* 400 Series HECI 1 */
+#define PCI_PRODUCT_INTEL_4HS_H_HECI_2 0x06e1 /* 400 Series HECI 2 */
+#define PCI_PRODUCT_INTEL_4HS_H_IDE_R 0x06e2 /* 400 Series IDE-R */
+#define PCI_PRODUCT_INTEL_4HS_H_KT 0x06e3 /* 400 Series KT */
+#define PCI_PRODUCT_INTEL_4HS_H_HECI_3 0x06e4 /* 400 Series HECI 3 */
+#define PCI_PRODUCT_INTEL_4HS_H_HECI_4 0x06e5 /* 400 Series HECI 4 */
+#define PCI_PRODUCT_INTEL_4HS_H_I2C_0 0x06e8 /* 400 Series I2C 0 */
+#define PCI_PRODUCT_INTEL_4HS_H_I2C_1 0x06e9 /* 400 Series I2C 1 */
+#define PCI_PRODUCT_INTEL_4HS_H_I2C_2 0x06ea /* 400 Series I2C 2 */
+#define PCI_PRODUCT_INTEL_4HS_H_I2C_3 0x06eb /* 400 Series I2C 3 */
+#define PCI_PRODUCT_INTEL_4HS_H_XHCI 0x06ed /* 400 Series USB 3.2 Gen 2x1 xHCI */
+#define PCI_PRODUCT_INTEL_4HS_H_SSRAM 0x06ef /* 400 Series Shared SRAM */
+#define PCI_PRODUCT_INTEL_4HS_H_CNVI_WIFI 0x06f0 /* 400 Series CNVi WiFi */
+#define PCI_PRODUCT_INTEL_4HS_H_SDXC 0x06f5 /* 400 Series SDXC */
+#define PCI_PRODUCT_INTEL_4HS_H_THERM 0x06f9 /* 400 Series Thermal */
+#define PCI_PRODUCT_INTEL_4HS_H_GSIP_2 0x06fb /* 400 Series GSPI 2 */
+#define PCI_PRODUCT_INTEL_4HS_H_ISH 0x06fc /* 400 Series Integrated Sensor Hub */
#define PCI_PRODUCT_INTEL_WIFI_LINK_6150_1 0x0885 /* Centrino Wireless-N 6150 */
#define PCI_PRODUCT_INTEL_WIFI_LINK_6150_2 0x0886 /* Centrino Wireless-N 6150 */
#define PCI_PRODUCT_INTEL_WIFI_LINK_2230_1 0x0887 /* Centrino Wireless-N 2230 */
@@ -4738,6 +4852,55 @@
#define PCI_PRODUCT_INTEL_82X58_IOXAPIC 0x342d /* 5520/5500/X58 IOxAPIC */
#define PCI_PRODUCT_INTEL_82X58_MISC 0x342e /* 5520/5500/X58 Misc */
#define PCI_PRODUCT_INTEL_82X58_THROTTLE 0x3438 /* 5520/5500/X58 Throttling */
+#define PCI_PRODUCT_INTEL_495_U_P_ESPI 0x3482 /* 495 Series U Premium eSPI */
+#define PCI_PRODUCT_INTEL_495_Y_P_ESPI 0x3487 /* 495 Series Y Premium eSPI */
+#define PCI_PRODUCT_INTEL_495_YU_P2SB 0x34a0 /* 495 Series P2SB */
+#define PCI_PRODUCT_INTEL_495_YU_PMC 0x34a1 /* 495 Series PMC */
+#define PCI_PRODUCT_INTEL_495_YU_SMB 0x34a3 /* 495 Series SMBus */
+#define PCI_PRODUCT_INTEL_495_YU_SPI 0x34a4 /* 495 Series SPI (FLASH) */
+#define PCI_PRODUCT_INTEL_495_YU_UART_0 0x34a8 /* 495 Series UART 0 */
+#define PCI_PRODUCT_INTEL_495_YU_UART_1 0x34a9 /* 495 Series UART 1 */
+#define PCI_PRODUCT_INTEL_495_YU_GSPI_0 0x34aa /* 495 Series GSPI 0 */
+#define PCI_PRODUCT_INTEL_495_YU_GSPI_1 0x34ab /* 495 Series GSPI 1 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_9 0x34b0 /* 495 Series PCIe Root Port 9 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_10 0x34b1 /* 495 Series PCIe Root Port 10 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_11 0x34b2 /* 495 Series PCIe Root Port 11 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_12 0x34b3 /* 495 Series PCIe Root Port 12 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_13 0x34b4 /* 495 Series PCIe Root Port 13 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_14 0x34b5 /* 495 Series PCIe Root Port 14 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_15 0x34b6 /* 495 Series PCIe Root Port 15 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_16 0x34b7 /* 495 Series PCIe Root Port 16 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_1 0x34b8 /* 495 Series PCIe Root Port 1 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_2 0x34b9 /* 495 Series PCIe Root Port 2 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_3 0x34ba /* 495 Series PCIe Root Port 3 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_4 0x34bb /* 495 Series PCIe Root Port 4 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_5 0x34bc /* 495 Series PCIe Root Port 5 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_6 0x34bd /* 495 Series PCIe Root Port 6 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_7 0x34be /* 495 Series PCIe Root Port 7 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_8 0x34bf /* 495 Series PCIe Root Port 8 */
+#define PCI_PRODUCT_INTEL_495_YU_PCIE_EMMC 0x34c4 /* 495 Series eMMC */
+#define PCI_PRODUCT_INTEL_495_YU_I2C_4 0x34c5 /* 495 Series I2C 4 */
+#define PCI_PRODUCT_INTEL_495_YU_I2C_5 0x34c6 /* 495 Series I2C 5 */
+#define PCI_PRODUCT_INTEL_495_YU_UART_2 0x34c7 /* 495 Series UART 2 */
+#define PCI_PRODUCT_INTEL_495_YU_AHCI 0x34d3 /* 495 Series SATA (AHCI) */
+#define PCI_PRODUCT_INTEL_495_YU_RAID 0x34d5 /* 495 Series SATA (RAID) */
+#define PCI_PRODUCT_INTEL_495_YU_RAID_P 0x34d7 /* 495 Series SATA (RAID) premium */
+#define PCI_PRODUCT_INTEL_495_YU_HECI_1 0x34e0 /* 495 Series HECI 1 */
+#define PCI_PRODUCT_INTEL_495_YU_HECI_2 0x34e1 /* 495 Series HECI 2 */
+#define PCI_PRODUCT_INTEL_495_YU_IDER 0x34e2 /* 495 Series IDE-R */
+#define PCI_PRODUCT_INTEL_495_YU_KT 0x34e3 /* 495 Series KT */
+#define PCI_PRODUCT_INTEL_495_YU_HECI_3 0x34e4 /* 495 Series HECI 3 */
+#define PCI_PRODUCT_INTEL_495_YU_HECI_4 0x34e5 /* 495 Series HECI 4 */
+#define PCI_PRODUCT_INTEL_495_YU_I2C_0 0x34e8 /* 495 Series I2C 0 */
+#define PCI_PRODUCT_INTEL_495_YU_I2C_1 0x34e9 /* 495 Series I2C 1 */
+#define PCI_PRODUCT_INTEL_495_YU_I2C_2 0x34ea /* 495 Series I2C 2 */
+#define PCI_PRODUCT_INTEL_495_YU_I2C_3 0x34eb /* 495 Series I2C 3 */
+#define PCI_PRODUCT_INTEL_495_YU_XHCI 0x34ed /* 495 Series USB 3.2 Gen 2x1 xHCI */
+#define PCI_PRODUCT_INTEL_495_YU_XDCI 0x34ee /* 495 Series USB 3.2 Gen 1x1 xDCI */
+#define PCI_PRODUCT_INTEL_495_YU_SSRAM 0x34ef /* 495 Series Shared SRAM */
+#define PCI_PRODUCT_INTEL_495_YU_SDXC 0x34f8 /* 495 Series SDXC */
+#define PCI_PRODUCT_INTEL_495_YU_GSPI_2 0x34fb /* 495 Series GSPI 2 */
+#define PCI_PRODUCT_INTEL_495_YU_ISH 0x34fc /* 495 Series ISH */
#define PCI_PRODUCT_INTEL_63XXESB_EXP_UP 0x3500 /* 63xxESB PCI Express Upstream Port */
#define PCI_PRODUCT_INTEL_63XXESB_PCIX 0x350c /* 63xxESB PCI Express to PCI-X Bridge */
#define PCI_PRODUCT_INTEL_63XXESB_EXP_DN_1 0x3510 /* 63xxESB PCI Express Downstream Port #1 */
@@ -5583,6 +5746,7 @@
#define PCI_PRODUCT_INTEL_3HS_U_I2C_2 0x9dea /* 300 Series I2C #2 */
#define PCI_PRODUCT_INTEL_3HS_U_I2C_3 0x9deb /* 300 Series I2C #3 */
#define PCI_PRODUCT_INTEL_3HS_U_XHCI 0x9ded /* 300 Series USB 3.1 xHCI */
+#define PCI_PRODUCT_INTEL_3HS_U_USBOTG 0x9dee /* 300 Series USB (OTG) */
#define PCI_PRODUCT_INTEL_3HS_U_SSRAM 0x9def /* 300 Series Shared SRAM */
#define PCI_PRODUCT_INTEL_WL_9560_1 0x9df0 /* Dual Band Wireless AC 9560 */
#define PCI_PRODUCT_INTEL_3HS_U_SDXC 0x9df5 /* 300 Series SDXC */
@@ -5595,6 +5759,55 @@
#define PCI_PRODUCT_INTEL_PINEVIEW_M_HB 0xa010 /* Pineview Host Bridge */
#define PCI_PRODUCT_INTEL_PINEVIEW_M_IGD 0xa011 /* Pineview Integrated Graphics Device */
#define PCI_PRODUCT_INTEL_PINEVIEW_M_IGD_1 0xa012 /* Pineview Integrated Graphics Device */
+#define PCI_PRODUCT_INTEL_5HS_LP_UP3_ESPI 0xa082 /* 500 Series UP3 eSPI */
+#define PCI_PRODUCT_INTEL_5HS_LP_UP4_ESPI 0xa087 /* 500 Series UP4 eSPI */
+#define PCI_PRODUCT_INTEL_5HS_LP_P2SB 0xa0a0 /* 500 Series P2SB */
+#define PCI_PRODUCT_INTEL_5HS_LP_PMC 0xa0a1 /* 500 Series PMC */
+#define PCI_PRODUCT_INTEL_5HS_LP_SMB 0xa0a3 /* 500 Series SMBus */
+#define PCI_PRODUCT_INTEL_5HS_LP_SPI 0xa0a4 /* 500 Series SPI (FLASH) */
+#define PCI_PRODUCT_INTEL_5HS_LP_TRACE 0xa0a6 /* 500 Series Trace Hub */
+#define PCI_PRODUCT_INTEL_5HS_LP_UART_0 0xa0a8 /* 500 Series UART 0 */
+#define PCI_PRODUCT_INTEL_5HS_LP_UART_1 0xa0a9 /* 500 Series UART 1 */
+#define PCI_PRODUCT_INTEL_5HS_LP_GSPI_0 0xa0aa /* 500 Series GSPI 0 */
+#define PCI_PRODUCT_INTEL_5HS_LP_GSPI_1 0xa0ab /* 500 Series GSPI 1 */
+#define PCI_PRODUCT_INTEL_5HS_LP_PCIE_9 0xa0b0 /* 500 Series PCIe 9 */
+#define PCI_PRODUCT_INTEL_5HS_LP_PCIE_10 0xa0b1 /* 500 Series PCIe 10 */
+#define PCI_PRODUCT_INTEL_5HS_LP_PCIE_11 0xa0b2 /* 500 Series PCIe 11 */
+#define PCI_PRODUCT_INTEL_5HS_LP_PCIE_12 0xa0b3 /* 500 Series PCIe 12 */
+#define PCI_PRODUCT_INTEL_5HS_LP_PCIE_1 0xa0b8 /* 500 Series PCIe 1 */
+#define PCI_PRODUCT_INTEL_5HS_LP_PCIE_2 0xa0b9 /* 500 Series PCIe 2 */
+#define PCI_PRODUCT_INTEL_5HS_LP_PCIE_3 0xa0ba /* 500 Series PCIe 3 */
+#define PCI_PRODUCT_INTEL_5HS_LP_PCIE_4 0xa0bb /* 500 Series PCIe 4 */
+#define PCI_PRODUCT_INTEL_5HS_LP_PCIE_5 0xa0bc /* 500 Series PCIe 5 */
+#define PCI_PRODUCT_INTEL_5HS_LP_PCIE_6 0xa0bd /* 500 Series PCIe 6 */
+#define PCI_PRODUCT_INTEL_5HS_LP_PCIE_7 0xa0be /* 500 Series PCIe 7 */
+#define PCI_PRODUCT_INTEL_5HS_LP_PCIE_8 0xa0bf /* 500 Series PCIe 8 */
+#define PCI_PRODUCT_INTEL_5HS_LP_I2C_4 0xa0c5 /* 500 Series I2C 4 */
+#define PCI_PRODUCT_INTEL_5HS_LP_I2C_5 0xa0c6 /* 500 Series I2C 5 */
+#define PCI_PRODUCT_INTEL_5HS_LP_UART_2 0xa0c7 /* 500 Series UART 2 */
+#define PCI_PRODUCT_INTEL_5HS_LP_HDA 0xa0c8 /* 500 Series HD Audio */
+#define PCI_PRODUCT_INTEL_5HS_LP_THC_0 0xa0d0 /* 500 Series THC 0 */
+#define PCI_PRODUCT_INTEL_5HS_LP_THC_1 0xa0d1 /* 500 Series THC 1 */
+#define PCI_PRODUCT_INTEL_5HS_LP_AHCI 0xa0d3 /* 500 Series SATA (AHCI) */
+#define PCI_PRODUCT_INTEL_5HS_LP_RAID 0xa0d5 /* 500 Series SATA (RAID) */
+#define PCI_PRODUCT_INTEL_5HS_LP_RAID_P 0xa0d7 /* 500 Series SATA (RAID) premium */
+#define PCI_PRODUCT_INTEL_5HS_LP_UART_3 0xa0da /* 500 Series UART 3 */
+#define PCI_PRODUCT_INTEL_5HS_LP_HECI_1 0xa0e0 /* 500 Series HECI 1 */
+#define PCI_PRODUCT_INTEL_5HS_LP_HECI_2 0xa0e1 /* 500 Series HECI 2 */
+#define PCI_PRODUCT_INTEL_5HS_LP_IDER 0xa0e2 /* 500 Series IDE-R */
+#define PCI_PRODUCT_INTEL_5HS_LP_KT 0xa0e3 /* 500 Series KT */
+#define PCI_PRODUCT_INTEL_5HS_LP_HECI_3 0xa0e4 /* 500 Series HECI 3 */
+#define PCI_PRODUCT_INTEL_5HS_LP_HECI_4 0xa0e5 /* 500 Series HECI 4 */
+#define PCI_PRODUCT_INTEL_5HS_LP_I2C_0 0xa0e8 /* 500 Series I2C 0 */
+#define PCI_PRODUCT_INTEL_5HS_LP_I2C_1 0xa0e9 /* 500 Series I2C 1 */
+#define PCI_PRODUCT_INTEL_5HS_LP_I2C_2 0xa0ea /* 500 Series I2C 2 */
+#define PCI_PRODUCT_INTEL_5HS_LP_I2C_3 0xa0eb /* 500 Series I2C 3 */
+#define PCI_PRODUCT_INTEL_5HS_LP_XHCI 0xa0ed /* 500 Series USB 3.2 Gen 2x1 xHCI */
+#define PCI_PRODUCT_INTEL_5HS_LP_XDCI 0xa0ee /* 500 Series USB 3.2 Gen 1x1 xDCI */
+#define PCI_PRODUCT_INTEL_5HS_LP_SSRAM 0xa0ef /* 500 Series Shared SRAM */
+#define PCI_PRODUCT_INTEL_5HS_LP_GSPI_2 0xa0fb /* 500 Series GSPI 2 */
+#define PCI_PRODUCT_INTEL_5HS_LP_ISH 0xa0fc /* 500 Series Integrated Sensor Hub */
+#define PCI_PRODUCT_INTEL_5HS_LP_GSPI_3 0xa0fd /* 500 Series GSPI 3 */
#define PCI_PRODUCT_INTEL_Z170_AHCI 0xa102 /* Z170 AHCI */
#define PCI_PRODUCT_INTEL_100SERIES_AHCI_2 0xa103 /* HM170, QM170 AHCI */
#define PCI_PRODUCT_INTEL_Z170_3RD_AHCI 0xa106 /* Z170 3rd Party RAID */
diff -r dec755563d79 -r 1794167836fd sys/dev/pci/pcidevs_data.h
--- a/sys/dev/pci/pcidevs_data.h Fri Nov 20 01:29:12 2020 +0000
+++ b/sys/dev/pci/pcidevs_data.h Fri Nov 20 01:29:46 2020 +0000
@@ -1,10 +1,10 @@
-/* $NetBSD: pcidevs_data.h,v 1.1406 2020/11/19 22:03:17 reinoud Exp $ */
+/* $NetBSD: pcidevs_data.h,v 1.1407 2020/11/20 01:29:46 msaitoh Exp $ */
/*
* THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
- * NetBSD: pcidevs,v 1.1420 2020/11/19 21:59:07 reinoud Exp
+ * NetBSD: pcidevs,v 1.1421 2020/11/20 01:29:12 msaitoh Exp
*/
/*
@@ -4987,26 +4987,126 @@
20673, 6530, 692, 1716, 2427, 0,
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_IVYBRIDGE_S_IGD_1,
20673, 6530, 692, 1716, 2427, 0,
+ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CMTLK_U_P_LPC,
+ 20677, 20556, 20683, 20685, 8673, 19090, 20695, 0,
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CMTLK_U_LPC,
- 20677, 20556, 20683, 8673, 19090, 20685, 0,
+ 20677, 20556, 20683, 8673, 19090, 20695, 0,
+ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CMTLK_P2SB,
+ 20677, 20556, 20700, 0,
+ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CMTLK_PMC,
+ 20677, 20556, 20705, 0,
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CMTLK_SMB,
20677, 20556, 8677, 0,
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_CMTLK_SPI,
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