[src/trunk]: src/sys/arch/arm/amlogic port-arm/55957: Odroid C2 can not acces...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/c04238be2673
branches:  trunk
changeset: 959001:c04238be2673
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Thu Jan 28 11:45:31 2021 +0000

description:
port-arm/55957: Odroid C2 can not access eMMC card

A few changes to clock setup:
 - Disable clock while changing dividers
 - Set / clear DDR flag before changing clock
 - Adjust TX/RX/core phases

diffstat:

 sys/arch/arm/amlogic/mesongx_mmc.c |  38 ++++++++++++++++++++------------------
 1 files changed, 20 insertions(+), 18 deletions(-)

diffs (81 lines):

diff -r fe46b07fadff -r c04238be2673 sys/arch/arm/amlogic/mesongx_mmc.c
--- a/sys/arch/arm/amlogic/mesongx_mmc.c        Thu Jan 28 10:36:27 2021 +0000
+++ b/sys/arch/arm/amlogic/mesongx_mmc.c        Thu Jan 28 11:45:31 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mesongx_mmc.c,v 1.13 2021/01/27 03:10:18 thorpej Exp $ */
+/* $NetBSD: mesongx_mmc.c,v 1.14 2021/01/28 11:45:31 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2019 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mesongx_mmc.c,v 1.13 2021/01/27 03:10:18 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mesongx_mmc.c,v 1.14 2021/01/28 11:45:31 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -496,6 +496,17 @@
        if (best_diff == INT_MAX)
                return ERANGE;
 
+       val = MMC_READ(sc, SD_EMMC_CFG);
+       val |= CFG_STOP_CLK;
+       MMC_WRITE(sc, SD_EMMC_CFG, val);
+
+       val = MMC_READ(sc, SD_EMMC_CFG);
+       if (ddr)
+               val |= CFG_DDR;
+       else
+               val &= ~CFG_DDR;
+       MMC_WRITE(sc, SD_EMMC_CFG, val);
+
        val = MMC_READ(sc, SD_EMMC_CLOCK);
        if (sc->sc_hwtype == MESONGX_MMC_V3)
                val |= CLOCK_CFG_V3_ALWAYS_ON;
@@ -504,15 +515,19 @@
        val &= ~CLOCK_CFG_RX_PHASE;
        val |= __SHIFTIN(0, CLOCK_CFG_RX_PHASE);
        val &= ~CLOCK_CFG_TX_PHASE;
-       val |= __SHIFTIN(2, CLOCK_CFG_TX_PHASE);
+       val |= __SHIFTIN(0, CLOCK_CFG_TX_PHASE);
        val &= ~CLOCK_CFG_CO_PHASE;
-       val |= __SHIFTIN(3, CLOCK_CFG_CO_PHASE);
+       val |= __SHIFTIN(2, CLOCK_CFG_CO_PHASE);
        val &= ~CLOCK_CFG_SRC;
        val |= __SHIFTIN(best_sel, CLOCK_CFG_SRC);
        val &= ~CLOCK_CFG_DIV;
        val |= __SHIFTIN(best_div, CLOCK_CFG_DIV);
        MMC_WRITE(sc, SD_EMMC_CLOCK, val);
 
+       val = MMC_READ(sc, SD_EMMC_CFG);
+       val &= ~CFG_STOP_CLK;
+       MMC_WRITE(sc, SD_EMMC_CFG, val);
+
        return 0;
 }
 
@@ -733,21 +748,8 @@
 mesongx_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr)
 {
        struct mesongx_mmc_softc * const sc = sch;
-       uint32_t val;
-       int error;
 
-       error = mesongx_mmc_set_clock(sc, freq, ddr);
-       if (error != 0)
-               return error;
-
-       val = MMC_READ(sc, SD_EMMC_CFG);
-       if (ddr)
-               val |= CFG_DDR; 
-       else
-               val &= ~CFG_DDR;
-       MMC_WRITE(sc, SD_EMMC_CFG, val);
-
-       return 0;
+       return mesongx_mmc_set_clock(sc, freq, ddr);
 }
 
 static int