[src/trunk]: src enable sun8icrypto on Allwinner H3 too.

[bad <bad%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/88ebcf97d522
branches:  trunk
changeset: 962044:88ebcf97d522
user:      bad <bad%NetBSD.org@localhost>
date:      Wed Apr 28 16:57:05 2021 +0000

description:
enable sun8icrypto on Allwinner H3 too.

Allwinner H3 needs a slower mod clock according to the Linux driver.

tested on NanoPi R1.

thanks jmcneill@ and riastradh@ for advice.

XXX pullup-9

diffstat:

 share/man/man4/man4.evbarm/sun8icrypto.4 |   6 ++--
 sys/arch/arm/sunxi/sun8i_crypto.c        |  47 +++++++++++++++++++++++++++----
 sys/arch/evbarm/conf/GENERIC             |   3 +-
 3 files changed, 45 insertions(+), 11 deletions(-)

diffs (153 lines):

diff -r d334c54b77ae -r 88ebcf97d522 share/man/man4/man4.evbarm/sun8icrypto.4
--- a/share/man/man4/man4.evbarm/sun8icrypto.4  Wed Apr 28 09:39:39 2021 +0000
+++ b/share/man/man4/man4.evbarm/sun8icrypto.4  Wed Apr 28 16:57:05 2021 +0000
@@ -1,4 +1,4 @@
-.\" $NetBSD: sun8icrypto.4,v 1.1 2021/04/27 21:13:38 nia Exp $
+.\" $NetBSD: sun8icrypto.4,v 1.2 2021/04/28 16:57:05 bad Exp $
 .\"
 .\" Copyright (c) 2021 The NetBSD Foundation, Inc.
 .\" All rights reserved.
@@ -24,7 +24,7 @@
 .\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 .\" POSSIBILITY OF SUCH DAMAGE.
 .\"
-.Dd April 25, 2021
+.Dd April 28, 2021
 .Dt SUN8ICRYPTO 4
 .Os
 .Sh NAME
@@ -36,7 +36,7 @@
 The
 .Nm
 driver provides support for the cryptographic processors on Allwinner
-A64 and H5 systems-on-a-chip.
+A64, H3 and H5 systems-on-a-chip.
 The Allwinner Crypto Engine is the successor to the earlier
 Allwinner Security System.
 .Pp
diff -r d334c54b77ae -r 88ebcf97d522 sys/arch/arm/sunxi/sun8i_crypto.c
--- a/sys/arch/arm/sunxi/sun8i_crypto.c Wed Apr 28 09:39:39 2021 +0000
+++ b/sys/arch/arm/sunxi/sun8i_crypto.c Wed Apr 28 16:57:05 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: sun8i_crypto.c,v 1.24 2021/04/24 13:01:35 riastradh Exp $      */
+/*     $NetBSD: sun8i_crypto.c,v 1.25 2021/04/28 16:57:05 bad Exp $    */
 
 /*-
  * Copyright (c) 2019 The NetBSD Foundation, Inc.
@@ -43,7 +43,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: sun8i_crypto.c,v 1.24 2021/04/24 13:01:35 riastradh Exp $");
+__KERNEL_RCSID(1, "$NetBSD: sun8i_crypto.c,v 1.25 2021/04/28 16:57:05 bad Exp $");
 
 #include <sys/types.h>
 #include <sys/param.h>
@@ -72,6 +72,28 @@
 #define        SUN8I_CRYPTO_RNGENTROPY 100 /* estimated bits per bit of entropy */
 #define        SUN8I_CRYPTO_RNGBYTES   PAGE_SIZE
 
+struct sun8i_crypto_config {
+       u_int   mod_rate;       /* module clock rate */
+};
+
+/*
+ * The module clock is set to 50 MHz on H3, 300 MHz otherwise.
+ * From Linux drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c:
+ * Module clock is lower on H3 than other SoC due to some DMA
+ * timeout occurring with high value.
+ */
+static const struct sun8i_crypto_config sun50i_a64_crypto_config = {
+       .mod_rate = 300*1000*1000,
+};
+
+static const struct sun8i_crypto_config sun50i_h5_crypto_config = {
+       .mod_rate = 300*1000*1000,
+};
+
+static const struct sun8i_crypto_config sun8i_h3_crypto_config = {
+       .mod_rate = 50*1000*1000,
+};
+
 struct sun8i_crypto_task;
 
 struct sun8i_crypto_buf {
@@ -86,6 +108,9 @@
        bus_space_handle_t              sc_bsh;
        bus_dma_tag_t                   sc_dmat;
        struct pool_cache               *sc_taskpool;
+
+       const struct sun8i_crypto_config *sc_cfg;
+
        kmutex_t                        sc_lock;
        struct sun8i_crypto_chan {
                struct sun8i_crypto_task        *cc_task;
@@ -319,8 +344,12 @@
     sun8i_crypto_match, sun8i_crypto_attach, NULL, NULL);
 
 static const struct device_compatible_entry compat_data[] = {
-       { .compat = "allwinner,sun50i-a64-crypto" },
-       { .compat = "allwinner,sun50i-h5-crypto" },
+       { .compat = "allwinner,sun50i-a64-crypto",
+         .data = &sun50i_a64_crypto_config },
+       { .compat = "allwinner,sun50i-h5-crypto",
+         .data = &sun50i_h5_crypto_config },
+       { .compat = "allwinner,sun8i-h3-crypto",
+         .data = &sun8i_h3_crypto_config },
        DEVICE_COMPAT_EOL
 };
 
@@ -343,6 +372,7 @@
        char intrstr[128];
        struct clk *clk;
        struct fdtbus_reset *rst;
+       u_int mod_rate;
 
        sc->sc_dev = self;
        sc->sc_dmat = faa->faa_dmat;
@@ -350,6 +380,7 @@
        sc->sc_taskpool = pool_cache_init(sizeof(struct sun8i_crypto_task),
            0, 0, 0, "sun8icry", NULL, IPL_VM,
            &sun8i_crypto_task_ctor, &sun8i_crypto_task_dtor, sc);
+       sc->sc_cfg = of_compatible_lookup(phandle, compat_data)->data;
        mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
        callout_init(&sc->sc_timeout, CALLOUT_MPSAFE);
        callout_setfunc(&sc->sc_timeout, &sun8i_crypto_timeout, sc);
@@ -388,14 +419,16 @@
                return;
        }
 
-       /* Get the module clock and set it to 300 MHz.  */
+       /* Get the module clock and set it. */
+       mod_rate = sc->sc_cfg->mod_rate;
        if ((clk = fdtbus_clock_get(phandle, "mod")) != NULL) {
                if (clk_enable(clk) != 0) {
                        aprint_error(": couldn't enable CE clock\n");
                        return;
                }
-               if (clk_set_rate(clk, 300*1000*1000) != 0) {
-                       aprint_error(": couldn't set CE clock to 300MHz\n");
+               if (clk_set_rate(clk, mod_rate) != 0) {
+                       aprint_error(": couldn't set CE clock to %d MHz\n",
+                           mod_rate / (1000 * 1000));
                        return;
                }
        }
diff -r d334c54b77ae -r 88ebcf97d522 sys/arch/evbarm/conf/GENERIC
--- a/sys/arch/evbarm/conf/GENERIC      Wed Apr 28 09:39:39 2021 +0000
+++ b/sys/arch/evbarm/conf/GENERIC      Wed Apr 28 16:57:05 2021 +0000
@@ -1,5 +1,5 @@
 #
-#      $NetBSD: GENERIC,v 1.95 2021/03/08 06:31:42 mlelstv Exp $
+#      $NetBSD: GENERIC,v 1.96 2021/04/28 16:57:05 bad Exp $
 #
 #      GENERIC ARM (aarch32) kernel
 #
@@ -399,6 +399,7 @@
 bcmrng*        at fdt?                 # Broadcom BCM283x RNG
 mesonrng*      at fdt?                 # Amlogic Meson RNG
 tirng*                 at fdt?                 # TI RNG
+sun8icrypto*   at fdt?                 # Allwinner Crypto Engine
 
 # Security ID EFUSE
 sunxisid*      at fdt? pass 4          # SID