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[src/netbsd-9]: src/sys/dev/nvmm/x86 Pull up following revision(s) (requested...
details: https://anonhg.NetBSD.org/src/rev/9ddc3de21a1e
branches: netbsd-9
changeset: 964085:9ddc3de21a1e
user: martin <martin%NetBSD.org@localhost>
date: Wed Aug 26 17:55:48 2020 +0000
description:
Pull up following revision(s) (requested by maxv in ticket #1058):
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.70
sys/dev/nvmm/x86/nvmm_x86.h: revision 1.19
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.69
sys/dev/nvmm/x86/nvmm_x86_vmx.c: revision 1.71
sys/dev/nvmm/x86/nvmm_x86_svm.c: revision 1.69
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.11
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.12
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.13
sys/dev/nvmm/x86/nvmm_x86.c: revision 1.14
Improve the CPUID emulation:
- Hide SGX*, PKU, WAITPKG, and SKINIT, because they are not supported.
- Hide HLE and RTM, part of TSX. Because TSX is just too buggy and we
cannot guarantee that it remains enabled in the guest (if for example
the host disables TSX while the guest is running). Nobody wants this
crap anyway, so bye-bye.
- Advertise FSREP_MOV, because no reason to hide it.
Hide OSPKE. NFC since the host never uses PKU, but still.
Improve the CPUID emulation on nvmm-intel:
- Limit the highest extended leaf.
- Limit 0x00000007 to ECX=0, for future-proofness.
nvmm-x86-svm: improve the CPUID emulation
Limit the hypervisor range, and properly handle each basic leaf until 0xD.
nvmm-x86: advertise the SERIALIZE instruction, available on future CPUs
nvmm-x86: improve the CPUID emulation
- x86-svm: explicitly handle 0x80000007 and 0x80000008. The latter
contains extended features we must filter out. Apply the same in
x86-vmx for symmetry.
- x86-svm: explicitly handle extended leaves until 0x8000001F, and
truncate to it.
diffstat:
sys/dev/nvmm/x86/nvmm_x86.c | 46 ++++++++++----
sys/dev/nvmm/x86/nvmm_x86.h | 6 +-
sys/dev/nvmm/x86/nvmm_x86_svm.c | 127 ++++++++++++++++++++++++++++++++++++++-
sys/dev/nvmm/x86/nvmm_x86_vmx.c | 52 +++++++++++++--
4 files changed, 201 insertions(+), 30 deletions(-)
diffs (truncated from 435 to 300 lines):
diff -r 95bf38098c00 -r 9ddc3de21a1e sys/dev/nvmm/x86/nvmm_x86.c
--- a/sys/dev/nvmm/x86/nvmm_x86.c Thu Aug 20 16:16:33 2020 +0000
+++ b/sys/dev/nvmm/x86/nvmm_x86.c Wed Aug 26 17:55:48 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86.c,v 1.7.4.3 2020/08/18 09:29:52 martin Exp $ */
+/* $NetBSD: nvmm_x86.c,v 1.7.4.4 2020/08/26 17:55:49 martin Exp $ */
/*
* Copyright (c) 2018-2020 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.7.4.3 2020/08/18 09:29:52 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86.c,v 1.7.4.4 2020/08/26 17:55:49 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -304,16 +304,16 @@
.ebx =
CPUID_SEF_FSGSBASE |
/* CPUID_SEF_TSC_ADJUST excluded */
- CPUID_SEF_SGX |
+ /* CPUID_SEF_SGX excluded */
CPUID_SEF_BMI1 |
- CPUID_SEF_HLE |
+ /* CPUID_SEF_HLE excluded */
/* CPUID_SEF_AVX2 excluded */
CPUID_SEF_FDPEXONLY |
CPUID_SEF_SMEP |
CPUID_SEF_BMI2 |
CPUID_SEF_ERMS |
/* CPUID_SEF_INVPCID excluded, but re-included in VMX */
- CPUID_SEF_RTM |
+ /* CPUID_SEF_RTM excluded */
/* CPUID_SEF_QM excluded */
CPUID_SEF_FPUCSDS |
/* CPUID_SEF_MPX excluded */
@@ -337,9 +337,9 @@
CPUID_SEF_PREFETCHWT1 |
/* CPUID_SEF_AVX512_VBMI excluded */
CPUID_SEF_UMIP |
- CPUID_SEF_PKU |
- CPUID_SEF_OSPKE |
- CPUID_SEF_WAITPKG |
+ /* CPUID_SEF_PKU excluded */
+ /* CPUID_SEF_OSPKE excluded */
+ /* CPUID_SEF_WAITPKG excluded */
/* CPUID_SEF_AVX512_VBMI2 excluded */
/* CPUID_SEF_CET_SS excluded */
CPUID_SEF_GFNI |
@@ -352,18 +352,18 @@
/* CPUID_SEF_RDPID excluded */
CPUID_SEF_CLDEMOTE |
CPUID_SEF_MOVDIRI |
- CPUID_SEF_MOVDIR64B |
- CPUID_SEF_SGXLC,
+ CPUID_SEF_MOVDIR64B,
+ /* CPUID_SEF_SGXLC excluded */
/* CPUID_SEF_PKS excluded */
.edx =
/* CPUID_SEF_AVX512_4VNNIW excluded */
/* CPUID_SEF_AVX512_4FMAPS excluded */
- /* CPUID_SEF_FSREP_MOV excluded */
+ CPUID_SEF_FSREP_MOV |
/* CPUID_SEF_AVX512_VP2INTERSECT excluded */
/* CPUID_SEF_SRBDS_CTRL excluded */
CPUID_SEF_MD_CLEAR |
/* CPUID_SEF_TSX_FORCE_ABORT excluded */
- /* CPUID_SEF_SERIALIZE excluded */
+ CPUID_SEF_SERIALIZE |
/* CPUID_SEF_HYBRID excluded */
/* CPUID_SEF_TSXLDTRK excluded */
/* CPUID_SEF_CET_IBT excluded */
@@ -391,7 +391,7 @@
/* CPUID_OSVW excluded */
CPUID_IBS |
CPUID_XOP |
- CPUID_SKINIT |
+ /* CPUID_SKINIT excluded */
CPUID_WDT |
CPUID_LWP |
CPUID_FMA4 |
@@ -421,6 +421,26 @@
CPUID_3DNOW
};
+const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000007 = {
+ .eax = 0,
+ .ebx = 0,
+ .ecx = 0,
+ .edx = CPUID_APM_ITSC
+};
+
+const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000008 = {
+ .eax = ~0,
+ .ebx =
+ CPUID_CAPEX_CLZERO |
+ /* CPUID_CAPEX_IRPERF excluded */
+ CPUID_CAPEX_XSAVEERPTR |
+ /* CPUID_CAPEX_RDPRU excluded */
+ /* CPUID_CAPEX_MCOMMIT excluded */
+ CPUID_CAPEX_WBNOINVD,
+ .ecx = ~0, /* TODO? */
+ .edx = 0
+};
+
bool
nvmm_x86_pat_validate(uint64_t val)
{
diff -r 95bf38098c00 -r 9ddc3de21a1e sys/dev/nvmm/x86/nvmm_x86.h
--- a/sys/dev/nvmm/x86/nvmm_x86.h Thu Aug 20 16:16:33 2020 +0000
+++ b/sys/dev/nvmm/x86/nvmm_x86.h Wed Aug 26 17:55:48 2020 +0000
@@ -1,7 +1,7 @@
-/* $NetBSD: nvmm_x86.h,v 1.15.4.1 2019/11/10 12:58:30 martin Exp $ */
+/* $NetBSD: nvmm_x86.h,v 1.15.4.2 2020/08/26 17:55:49 martin Exp $ */
/*
- * Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
+ * Copyright (c) 2018-2020 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
@@ -320,6 +320,8 @@
extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000001;
extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_00000007;
extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000001;
+extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000007;
+extern const struct nvmm_x86_cpuid_mask nvmm_cpuid_80000008;
bool nvmm_x86_pat_validate(uint64_t);
#endif
diff -r 95bf38098c00 -r 9ddc3de21a1e sys/dev/nvmm/x86/nvmm_x86_svm.c
--- a/sys/dev/nvmm/x86/nvmm_x86_svm.c Thu Aug 20 16:16:33 2020 +0000
+++ b/sys/dev/nvmm/x86/nvmm_x86_svm.c Wed Aug 26 17:55:48 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86_svm.c,v 1.46.4.8 2020/08/18 09:29:52 martin Exp $ */
+/* $NetBSD: nvmm_x86_svm.c,v 1.46.4.9 2020/08/26 17:55:48 martin Exp $ */
/*
* Copyright (c) 2018-2019 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.46.4.8 2020/08/18 09:29:52 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.46.4.9 2020/08/26 17:55:48 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -783,7 +783,23 @@
vmcb->ctrl.intr &= ~VMCB_CTRL_INTR_SHADOW;
}
+#define SVM_CPUID_MAX_BASIC 0xD
#define SVM_CPUID_MAX_HYPERVISOR 0x40000000
+#define SVM_CPUID_MAX_EXTENDED 0x8000001F
+static uint32_t svm_cpuid_max_basic __read_mostly;
+static uint32_t svm_cpuid_max_extended __read_mostly;
+
+static void
+svm_inkernel_exec_cpuid(struct svm_cpudata *cpudata, uint64_t eax, uint64_t ecx)
+{
+ u_int descs[4];
+
+ x86_cpuid2(eax, ecx, descs);
+ cpudata->vmcb->state.rax = descs[0];
+ cpudata->gprs[NVMM_X64_GPR_RBX] = descs[1];
+ cpudata->gprs[NVMM_X64_GPR_RCX] = descs[2];
+ cpudata->gprs[NVMM_X64_GPR_RDX] = descs[3];
+}
static void
svm_inkernel_handle_cpuid(struct nvmm_cpu *vcpu, uint64_t eax, uint64_t ecx)
@@ -791,7 +807,27 @@
struct svm_cpudata *cpudata = vcpu->cpudata;
uint64_t cr4;
+ if (eax < 0x40000000) {
+ if (__predict_false(eax > svm_cpuid_max_basic)) {
+ eax = svm_cpuid_max_basic;
+ svm_inkernel_exec_cpuid(cpudata, eax, ecx);
+ }
+ } else if (eax < 0x80000000) {
+ if (__predict_false(eax > SVM_CPUID_MAX_HYPERVISOR)) {
+ eax = svm_cpuid_max_basic;
+ svm_inkernel_exec_cpuid(cpudata, eax, ecx);
+ }
+ } else {
+ if (__predict_false(eax > svm_cpuid_max_extended)) {
+ eax = svm_cpuid_max_basic;
+ svm_inkernel_exec_cpuid(cpudata, eax, ecx);
+ }
+ }
+
switch (eax) {
+ case 0x00000000:
+ cpudata->vmcb->state.rax = svm_cpuid_max_basic;
+ break;
case 0x00000001:
cpudata->vmcb->state.rax &= nvmm_cpuid_00000001.eax;
@@ -821,10 +857,20 @@
cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
break;
case 0x00000007: /* Structured Extended Features */
- cpudata->vmcb->state.rax &= nvmm_cpuid_00000007.eax;
- cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_00000007.ebx;
- cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000007.ecx;
- cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000007.edx;
+ switch (ecx) {
+ case 0:
+ cpudata->vmcb->state.rax = 0;
+ cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_00000007.ebx;
+ cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000007.ecx;
+ cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000007.edx;
+ break;
+ default:
+ cpudata->vmcb->state.rax = 0;
+ cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
+ break;
+ }
break;
case 0x00000008: /* Empty */
case 0x00000009: /* Empty */
@@ -879,12 +925,74 @@
memcpy(&cpudata->gprs[NVMM_X64_GPR_RDX], " ___", 4);
break;
+ case 0x80000000:
+ cpudata->vmcb->state.rax = svm_cpuid_max_extended;
+ break;
case 0x80000001:
cpudata->vmcb->state.rax &= nvmm_cpuid_80000001.eax;
cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000001.ebx;
cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_80000001.ecx;
cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_80000001.edx;
break;
+ case 0x80000002: /* Extended Processor Name String */
+ case 0x80000003: /* Extended Processor Name String */
+ case 0x80000004: /* Extended Processor Name String */
+ case 0x80000005: /* L1 Cache and TLB Information */
+ case 0x80000006: /* L2 Cache and TLB and L3 Cache Information */
+ break;
+ case 0x80000007: /* Processor Power Management and RAS Capabilities */
+ cpudata->vmcb->state.rax &= nvmm_cpuid_80000007.eax;
+ cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000007.ebx;
+ cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_80000007.ecx;
+ cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_80000007.edx;
+ break;
+ case 0x80000008: /* Processor Capacity Parameters and Ext Feat Ident */
+ cpudata->vmcb->state.rax &= nvmm_cpuid_80000008.eax;
+ cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000008.ebx;
+ cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_80000008.ecx;
+ cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_80000008.edx;
+ break;
+ case 0x80000009: /* Empty */
+ case 0x8000000A: /* SVM Features */
+ case 0x8000000B: /* Empty */
+ case 0x8000000C: /* Empty */
+ case 0x8000000D: /* Empty */
+ case 0x8000000E: /* Empty */
+ case 0x8000000F: /* Empty */
+ case 0x80000010: /* Empty */
+ case 0x80000011: /* Empty */
+ case 0x80000012: /* Empty */
+ case 0x80000013: /* Empty */
+ case 0x80000014: /* Empty */
+ case 0x80000015: /* Empty */
+ case 0x80000016: /* Empty */
+ case 0x80000017: /* Empty */
+ case 0x80000018: /* Empty */
+ cpudata->vmcb->state.rax = 0;
+ cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
+ break;
+ case 0x80000019: /* TLB Characteristics for 1GB pages */
+ case 0x8000001A: /* Instruction Optimizations */
+ break;
+ case 0x8000001B: /* Instruction-Based Sampling Capabilities */
+ case 0x8000001C: /* Lightweight Profiling Capabilities */
+ cpudata->vmcb->state.rax = 0;
+ cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
+ break;
+ case 0x8000001D: /* Cache Topology Information */
+ case 0x8000001E: /* Processor Topology Information */
+ break; /* TODO? */
+ case 0x8000001F: /* Encrypted Memory Capabilities */
+ cpudata->vmcb->state.rax = 0;
+ cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
+ cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
+ break;
+
default:
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