[src/netbsd-9]: src/usr.sbin/cpuctl/arch Pull up following revision(s) (reque...

[martin <martin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/f999d7e22a73
branches:  netbsd-9
changeset: 963024:f999d7e22a73
user:      martin <martin%NetBSD.org@localhost>
date:      Thu Sep 26 18:47:14 2019 +0000

description:
Pull up following revision(s) (requested by msaitoh in ticket #241):

        sys/arch/x86/include/specialreg.h: revision 1.152
        sys/arch/x86/include/specialreg.h: revision 1.153
        usr.sbin/cpuctl/arch/i386.c: revision 1.105
        sys/arch/x86/x86/spectre.c: revision 1.30
        sys/arch/x86/include/specialreg.h: revision 1.151

Add definitions of AMD's CPUID Fn8000_0008 %ebx.
Decode AMD's CPUID Fn8000_0008 %ebx.
Use macro.
Add MCOMMIT instruction.
Define CPUID_CAPEX_FLAGS's bit 10 correctly.

diffstat:

 sys/arch/x86/include/specialreg.h |  35 ++++++++++++++++++++++++++++++++++-
 sys/arch/x86/x86/spectre.c        |   6 +++---
 usr.sbin/cpuctl/arch/i386.c       |  14 ++++++++++----
 3 files changed, 47 insertions(+), 8 deletions(-)

diffs (113 lines):

diff -r 662a4680028a -r f999d7e22a73 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Wed Sep 25 15:47:36 2019 +0000
+++ b/sys/arch/x86/include/specialreg.h Thu Sep 26 18:47:14 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.150 2019/07/26 10:03:40 msaitoh Exp $ */
+/*     $NetBSD: specialreg.h,v 1.150.2.1 2019/09/26 18:47:14 martin Exp $      */
 
 /*
  * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -712,6 +712,39 @@
        "\11" "TSC"     "\12" "CPB"     "\13" "EffFreq" "\14" "PROCFI"        \
        "\15" "PROCPR"  "\16" "CONNSTBY" "\17" "RAPL"
 
+/*
+ * AMD Processor Capacity Parameters and Extended Features
+ * CPUID Fn8000_0008
+ * %eax: Long Mode Size Identifiers
+ * %ebx: Extended Feature Identifiers
+ * %ecx: Size Identifiers
+ */
+
+/* %ebx */
+#define CPUID_CAPEX_CLZERO     __BIT(0)        /* CLZERO instruction */
+#define CPUID_CAPEX_IRPERF     __BIT(1)        /* InstRetCntMsr */
+#define CPUID_CAPEX_XSAVEERPTR __BIT(2)        /* RstrFpErrPtrs by XRSTOR */
+#define CPUID_CAPEX_RDPRU      __BIT(4)        /* RDPRU instruction */
+#define CPUID_CAPEX_MCOMMIT    __BIT(8)        /* MCOMMIT instruction */
+#define CPUID_CAPEX_WBNOINVD   __BIT(9)        /* WBNOINVD instruction */
+#define CPUID_CAPEX_IBPB       __BIT(12)       /* Speculation Control IBPB */
+#define CPUID_CAPEX_IBRS       __BIT(14)       /* Speculation Control IBRS */
+#define CPUID_CAPEX_STIBP      __BIT(15)       /* Speculation Control STIBP */
+#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16)    /* IBRS always on mode */
+#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17)   /* STIBP always on mode */
+#define CPUID_CAPEX_PREFER_IBRS        __BIT(18)       /* IBRS preferred */
+#define CPUID_CAPEX_SSBD       __BIT(24)       /* Speculation Control SSBD */
+#define CPUID_CAPEX_VIRT_SSBD  __BIT(25)       /* Virt Spec Control SSBD */
+#define CPUID_CAPEX_SSB_NO     __BIT(26)       /* SSBD not required */
+
+#define CPUID_CAPEX_FLAGS      "\20"                                    \
+       "\1CLZERO"      "\2IRPERF"      "\3XSAVEERPTR"                   \
+       "\5RDPRU"                       "\7B6"                           \
+       "\11MCOMMIT"    "\12WBNOINVD"   "\13B10"                         \
+       "\15IBPB"       "\16B13"        "\17IBRS"       "\20STIBP"       \
+       "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \
+       "\31SSBD"       "\32VIRT_SSBD"  "\33SSB_NO"
+
 /* AMD Fn8000000a %edx features (SVM features) */
 #define CPUID_AMD_SVM_NP               0x00000001
 #define CPUID_AMD_SVM_LbrVirt          0x00000002
diff -r 662a4680028a -r f999d7e22a73 sys/arch/x86/x86/spectre.c
--- a/sys/arch/x86/x86/spectre.c        Wed Sep 25 15:47:36 2019 +0000
+++ b/sys/arch/x86/x86/spectre.c        Thu Sep 26 18:47:14 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: spectre.c,v 1.29 2019/06/01 06:54:28 maxv Exp $        */
+/*     $NetBSD: spectre.c,v 1.29.2.1 2019/09/26 18:47:14 martin Exp $  */
 
 /*
  * Copyright (c) 2018-2019 NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: spectre.c,v 1.29 2019/06/01 06:54:28 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: spectre.c,v 1.29.2.1 2019/09/26 18:47:14 martin Exp $");
 
 #include "opt_spectre.h"
 
@@ -435,7 +435,7 @@
                                break;
                        }
                        x86_cpuid(0x80000008, descs);
-                       if (descs[1] & __BIT(26)) {
+                       if (descs[1] & CPUID_CAPEX_SSB_NO) {
                                /* Not vulnerable to SpectreV4. */
                                v4_mitigation_method = V4_MITIGATION_AMD_SSB_NO;
                                return;
diff -r 662a4680028a -r f999d7e22a73 usr.sbin/cpuctl/arch/i386.c
--- a/usr.sbin/cpuctl/arch/i386.c       Wed Sep 25 15:47:36 2019 +0000
+++ b/usr.sbin/cpuctl/arch/i386.c       Thu Sep 26 18:47:14 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: i386.c,v 1.104 2019/07/26 10:03:40 msaitoh Exp $       */
+/*     $NetBSD: i386.c,v 1.104.2.1 2019/09/26 18:47:14 martin Exp $    */
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include <sys/cdefs.h>
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.104 2019/07/26 10:03:40 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.104.2.1 2019/09/26 18:47:14 martin Exp $");
 #endif /* not lint */
 
 #include <sys/types.h>
@@ -2292,10 +2292,16 @@
                        ci->ci_max_ext_cpuid = descs[0];
                else
                        ci->ci_max_ext_cpuid = 0;
-               if (descs[0] >= 0x80000007)
+               if (ci->ci_max_ext_cpuid >= 0x80000007)
                        powernow_probe(ci);
 
-               if ((descs[0] >= 0x8000000a)
+               if (ci->ci_max_ext_cpuid >= 0x80000008) {
+                       x86_cpuid(0x80000008, descs);
+                       print_bits(cpuname, "AMD Extended features",
+                           CPUID_CAPEX_FLAGS, descs[1]);
+               }
+
+               if ((ci->ci_max_ext_cpuid >= 0x8000000a)
                    && (ci->ci_feat_val[3] & CPUID_SVM) != 0) {
                        x86_cpuid(0x8000000a, descs);
                        aprint_verbose("%s: SVM Rev. %d\n", cpuname,