[src/netbsd-9]: src/sys/arch/arm/sunxi Pull up following revision(s) (request...

[martin <martin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/2df821a50d1b
branches:  netbsd-9
changeset: 962952:2df821a50d1b
user:      martin <martin%NetBSD.org@localhost>
date:      Fri Sep 06 19:54:23 2019 +0000

description:
Pull up following revision(s) (requested by bouyer in ticket #187):

        sys/arch/arm/sunxi/sunxi_mmc.c: revision 1.37

The mmc module clock needs to be doubled only for 8bits DDR mode on old
timing hardware.

This makes the lime2-eemc works in 4bits DDR52 mode.

diffstat:

 sys/arch/arm/sunxi/sunxi_mmc.c |  21 ++++++++++++++-------
 1 files changed, 14 insertions(+), 7 deletions(-)

diffs (79 lines):

diff -r 28255812c432 -r 2df821a50d1b sys/arch/arm/sunxi/sunxi_mmc.c
--- a/sys/arch/arm/sunxi/sunxi_mmc.c    Fri Sep 06 19:51:54 2019 +0000
+++ b/sys/arch/arm/sunxi/sunxi_mmc.c    Fri Sep 06 19:54:23 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_mmc.c,v 1.33 2019/05/27 23:27:01 jmcneill Exp $ */
+/* $NetBSD: sunxi_mmc.c,v 1.33.2.1 2019/09/06 19:54:23 martin Exp $ */
 
 /*-
  * Copyright (c) 2014-2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
 #include "opt_sunximmc.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.33 2019/05/27 23:27:01 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.33.2.1 2019/09/06 19:54:23 martin Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -480,7 +480,7 @@
 }
 
 static int
-sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq, bool ddr)
+sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq, bool ddr, bool dbl)
 {
        const struct sunxi_mmc_delay *delays;
        int error, timing = SUNXI_MMC_TIMING_400K;
@@ -506,7 +506,7 @@
                        return EINVAL;
        }
 
-       error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << ddr);
+       error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << dbl);
        if (error != 0)
                return error;
 
@@ -554,7 +554,7 @@
 
        sunxi_mmc_host_reset(sc);
        sunxi_mmc_bus_width(sc, 1);
-       sunxi_mmc_set_clock(sc, 400, false);
+       sunxi_mmc_set_clock(sc, 400, false, false);
 
        if (sc->sc_pwrseq)
                fdtbus_mmc_pwrseq_post_power_on(sc->sc_pwrseq);
@@ -815,6 +815,7 @@
        struct sunxi_mmc_softc *sc = sch;
        uint32_t clkcr, gctrl, ntsr;
        const u_int flags = sc->sc_config->flags;
+       bool dbl = 0;
 
        clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR);
        if (clkcr & SUNXI_MMC_CLKCR_CARDCLKON) {
@@ -832,9 +833,15 @@
        }
 
        if (freq) {
+               /* For 8bits ddr in old timing modes, and all ddr in new
+                * timing modes, the module clock has to be 2x the card clock.
+                */
+               if (ddr && ((flags & SUNXI_MMC_FLAG_NEW_TIMINGS) ||
+                   sc->sc_mmc_width == 8))
+                       dbl = 1;
 
                clkcr &= ~SUNXI_MMC_CLKCR_DIV;
-               clkcr |= __SHIFTIN(ddr, SUNXI_MMC_CLKCR_DIV);
+               clkcr |= __SHIFTIN(dbl, SUNXI_MMC_CLKCR_DIV);
                MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr);
 
                if (flags & SUNXI_MMC_FLAG_NEW_TIMINGS) {
@@ -856,7 +863,7 @@
                        gctrl &= ~SUNXI_MMC_GCTRL_DDR_MODE;
                MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl);
 
-               if (sunxi_mmc_set_clock(sc, freq, ddr) != 0)
+               if (sunxi_mmc_set_clock(sc, freq, ddr, dbl) != 0)
                        return 1;
 
                clkcr |= SUNXI_MMC_CLKCR_CARDCLKON;