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[src/netbsd-9]: src/sys/dev/pci Pull up following revision(s) (requested by j...
details: https://anonhg.NetBSD.org/src/rev/41de86c4b3a0
branches: netbsd-9
changeset: 963819:41de86c4b3a0
user: martin <martin%NetBSD.org@localhost>
date: Tue Apr 28 15:44:06 2020 +0000
description:
Pull up following revision(s) (requested by jmcneill in ticket #858):
sys/dev/pci/if_mcx.c: revision 1.13
mcx: sync with OpenBSD sys/dev/pci/if_mcx.c r1.44
1.44:
Fix typo which could lead into a double free
1.43:
Commands that create objects return a 24 bit object ID, so mask off the
high 8 bits of the value we extract, in case the firmware leaves junk there.
Hrvoje Popovski has seen this with newer firmware on a ConnectX 5 card,
which now works properly.
1.42:
Increase the completion queue size to prevent overflow. Under reasonably
unlikely circumstances - lots of single-fragment packets being sent, a
significant number of packets being received, while the interrupt handler
was unable to process the completion queue - the completion queue could
overflow, which would result in the interface locking up.
1.41:
Check if we've reached the end of the current mailbox before writing past
the end of it, rather than after. Now we can actually allocate queues
big enough to need multiple mailboxes.
1.40:
Don't call mcx_intr() from mcx_cmdq_poll(); this was a leftover from early
development that I forgot about, but turns out to be a potential race with
the actual interrupt handler.
1.39:
fix previous: use the correct offset for sq/rq creation, and don't
reset the mbox counter to 0 after calculating it.
1.38:
Add a helper function for writing physical addresses for queues into
command queue mailboxes, and use this for all queue setup commands.
Previously we just assumed the addresses would fit in the first mailbox,
which is currently true but may not be for much longer.
1.37:
(skipped)
1.36:
The event queue consumer counter also needs to be unsigned like the others.
1.35:
try to make if_baudrate look plausible.
this updates the eth proto capability map so it records the baudrate
against the different link types and their media, and then reads
it when the link state changes.
1.34:
(skipped)
diffstat:
sys/dev/pci/if_mcx.c | 283 +++++++++++++++++++++++++++++---------------------
1 files changed, 166 insertions(+), 117 deletions(-)
diffs (truncated from 505 to 300 lines):
diff -r 7644c0e4f0da -r 41de86c4b3a0 sys/dev/pci/if_mcx.c
--- a/sys/dev/pci/if_mcx.c Mon Apr 27 14:57:31 2020 +0000
+++ b/sys/dev/pci/if_mcx.c Tue Apr 28 15:44:06 2020 +0000
@@ -1,5 +1,5 @@
-/* $NetBSD: if_mcx.c,v 1.1.2.9 2020/03/01 12:47:10 martin Exp $ */
-/* $OpenBSD: if_mcx.c,v 1.33 2019/09/12 04:23:59 jmatthew Exp $ */
+/* $NetBSD: if_mcx.c,v 1.1.2.10 2020/04/28 15:44:06 martin Exp $ */
+/* $OpenBSD: if_mcx.c,v 1.44 2020/04/24 07:28:37 mestre Exp $ */
/*
* Copyright (c) 2017 David Gwynne <dlg%openbsd.org@localhost>
@@ -82,7 +82,7 @@
/* queue sizes */
#define MCX_LOG_EQ_SIZE 6 /* one page */
-#define MCX_LOG_CQ_SIZE 11
+#define MCX_LOG_CQ_SIZE 12
#define MCX_LOG_RQ_SIZE 10
#define MCX_LOG_SQ_SIZE 11
@@ -154,33 +154,33 @@
#define MCX_REG_PPCNT 0x5008
#define MCX_REG_MCIA 0x9014
-#define MCX_ETHER_CAP_SGMII (1 << 0)
-#define MCX_ETHER_CAP_1000_KX (1 << 1)
-#define MCX_ETHER_CAP_10G_CX4 (1 << 2)
-#define MCX_ETHER_CAP_10G_KX4 (1 << 3)
-#define MCX_ETHER_CAP_10G_KR (1 << 4)
-#define MCX_ETHER_CAP_20G_KR2 (1 << 5)
-#define MCX_ETHER_CAP_40G_CR4 (1 << 6)
-#define MCX_ETHER_CAP_40G_KR4 (1 << 7)
-#define MCX_ETHER_CAP_56G_R4 (1 << 8)
-#define MCX_ETHER_CAP_10G_CR (1 << 12)
-#define MCX_ETHER_CAP_10G_SR (1 << 13)
-#define MCX_ETHER_CAP_10G_LR (1 << 14)
-#define MCX_ETHER_CAP_40G_SR4 (1 << 15)
-#define MCX_ETHER_CAP_40G_LR4 (1 << 16)
-#define MCX_ETHER_CAP_50G_SR2 (1 << 18)
-#define MCX_ETHER_CAP_100G_CR4 (1 << 20)
-#define MCX_ETHER_CAP_100G_SR4 (1 << 21)
-#define MCX_ETHER_CAP_100G_KR4 (1 << 22)
-#define MCX_ETHER_CAP_100G_LR4 (1 << 23)
-#define MCX_ETHER_CAP_100_TX (1 << 24)
-#define MCX_ETHER_CAP_1000_T (1 << 25)
-#define MCX_ETHER_CAP_10G_T (1 << 26)
-#define MCX_ETHER_CAP_25G_CR (1 << 27)
-#define MCX_ETHER_CAP_25G_KR (1 << 28)
-#define MCX_ETHER_CAP_25G_SR (1 << 29)
-#define MCX_ETHER_CAP_50G_CR2 (1 << 30)
-#define MCX_ETHER_CAP_50G_KR2 (1 << 31)
+#define MCX_ETHER_CAP_SGMII 0
+#define MCX_ETHER_CAP_1000_KX 1
+#define MCX_ETHER_CAP_10G_CX4 2
+#define MCX_ETHER_CAP_10G_KX4 3
+#define MCX_ETHER_CAP_10G_KR 4
+#define MCX_ETHER_CAP_20G_KR2 5
+#define MCX_ETHER_CAP_40G_CR4 6
+#define MCX_ETHER_CAP_40G_KR4 7
+#define MCX_ETHER_CAP_56G_R4 8
+#define MCX_ETHER_CAP_10G_CR 12
+#define MCX_ETHER_CAP_10G_SR 13
+#define MCX_ETHER_CAP_10G_LR 14
+#define MCX_ETHER_CAP_40G_SR4 15
+#define MCX_ETHER_CAP_40G_LR4 16
+#define MCX_ETHER_CAP_50G_SR2 18
+#define MCX_ETHER_CAP_100G_CR4 20
+#define MCX_ETHER_CAP_100G_SR4 21
+#define MCX_ETHER_CAP_100G_KR4 22
+#define MCX_ETHER_CAP_100G_LR4 23
+#define MCX_ETHER_CAP_100_TX 24
+#define MCX_ETHER_CAP_1000_T 25
+#define MCX_ETHER_CAP_10G_T 26
+#define MCX_ETHER_CAP_25G_CR 27
+#define MCX_ETHER_CAP_25G_KR 28
+#define MCX_ETHER_CAP_25G_SR 29
+#define MCX_ETHER_CAP_50G_CR2 30
+#define MCX_ETHER_CAP_50G_KR2 31
#define MCX_PAGE_SHIFT 12
#define MCX_PAGE_SIZE (1 << MCX_PAGE_SHIFT)
@@ -1970,7 +1970,7 @@
struct mcx_dmamem sc_doorbell_mem;
int sc_eqn;
- int sc_eq_cons;
+ uint32_t sc_eq_cons;
struct mcx_dmamem sc_eq_mem;
int sc_hardmtu;
@@ -2146,41 +2146,47 @@
{ PCI_VENDOR_MELLANOX, PCI_PRODUCT_MELLANOX_MT28800 },
};
-static const uint64_t mcx_eth_cap_map[] = {
- IFM_1000_SGMII,
- IFM_1000_KX,
- IFM_10G_CX4,
- IFM_10G_KX4,
- IFM_10G_KR,
- IFM_20G_KR2,
- IFM_40G_CR4,
- IFM_40G_KR4,
- IFM_56G_R4,
- 0,
- 0,
- 0,
- IFM_10G_CR1,
- IFM_10G_SR,
- IFM_10G_LR,
- IFM_40G_SR4,
- IFM_40G_LR4,
- 0,
- IFM_50G_SR2,
- 0,
- IFM_100G_CR4,
- IFM_100G_SR4,
- IFM_100G_KR4,
- IFM_100G_LR4,
- IFM_100_TX,
- IFM_1000_T,
- IFM_10G_T,
- IFM_25G_CR,
- IFM_25G_KR,
- IFM_25G_SR,
- IFM_50G_CR2,
- IFM_50G_KR2
+struct mcx_eth_proto_capability {
+ uint64_t cap_media;
+ uint64_t cap_baudrate;
};
+static const struct mcx_eth_proto_capability mcx_eth_cap_map[] = {
+ [MCX_ETHER_CAP_SGMII] = { IFM_1000_SGMII, IF_Gbps(1) },
+ [MCX_ETHER_CAP_1000_KX] = { IFM_1000_KX, IF_Gbps(1) },
+ [MCX_ETHER_CAP_10G_CX4] = { IFM_10G_CX4, IF_Gbps(10) },
+ [MCX_ETHER_CAP_10G_KX4] = { IFM_10G_KX4, IF_Gbps(10) },
+ [MCX_ETHER_CAP_10G_KR] = { IFM_10G_KR, IF_Gbps(10) },
+ [MCX_ETHER_CAP_20G_KR2] = { IFM_20G_KR2, IF_Gbps(20) },
+ [MCX_ETHER_CAP_40G_CR4] = { IFM_40G_CR4, IF_Gbps(40) },
+ [MCX_ETHER_CAP_40G_KR4] = { IFM_40G_KR4, IF_Gbps(40) },
+ [MCX_ETHER_CAP_56G_R4] = { IFM_56G_R4, IF_Gbps(56) },
+ [MCX_ETHER_CAP_10G_CR] = { IFM_10G_CR1, IF_Gbps(10) },
+ [MCX_ETHER_CAP_10G_SR] = { IFM_10G_SR, IF_Gbps(10) },
+ [MCX_ETHER_CAP_10G_LR] = { IFM_10G_LR, IF_Gbps(10) },
+ [MCX_ETHER_CAP_40G_SR4] = { IFM_40G_SR4, IF_Gbps(40) },
+ [MCX_ETHER_CAP_40G_LR4] = { IFM_40G_LR4, IF_Gbps(40) },
+ [MCX_ETHER_CAP_50G_SR2] = { IFM_50G_SR2, IF_Gbps(50) },
+ [MCX_ETHER_CAP_100G_CR4] = { IFM_100G_CR4, IF_Gbps(100) },
+ [MCX_ETHER_CAP_100G_SR4] = { IFM_100G_SR4, IF_Gbps(100) },
+ [MCX_ETHER_CAP_100G_KR4] = { IFM_100G_KR4, IF_Gbps(100) },
+ [MCX_ETHER_CAP_100G_LR4] = { IFM_100G_LR4, IF_Gbps(100) },
+ [MCX_ETHER_CAP_100_TX] = { IFM_100_TX, IF_Mbps(100) },
+ [MCX_ETHER_CAP_1000_T] = { IFM_1000_T, IF_Gbps(1) },
+ [MCX_ETHER_CAP_10G_T] = { IFM_10G_T, IF_Gbps(10) },
+ [MCX_ETHER_CAP_25G_CR] = { IFM_25G_CR, IF_Gbps(25) },
+ [MCX_ETHER_CAP_25G_KR] = { IFM_25G_KR, IF_Gbps(25) },
+ [MCX_ETHER_CAP_25G_SR] = { IFM_25G_SR, IF_Gbps(25) },
+ [MCX_ETHER_CAP_50G_CR2] = { IFM_50G_CR2, IF_Gbps(50) },
+ [MCX_ETHER_CAP_50G_KR2] = { IFM_50G_KR2, IF_Gbps(50) },
+};
+
+static int
+mcx_get_id(uint32_t val)
+{
+ return be32toh(val) & 0x00ffffff;
+}
+
static int
mcx_match(device_t parent, cfdata_t cf, void *aux)
{
@@ -2557,11 +2563,8 @@
0, MCX_DMA_LEN(&sc->sc_cmdq_mem), BUS_DMASYNC_POSTRW);
if ((cqe->cq_status & MCX_CQ_STATUS_OWN_MASK) ==
- MCX_CQ_STATUS_OWN_SW) {
- if (sc->sc_eqn != 0)
- mcx_intr(sc);
+ MCX_CQ_STATUS_OWN_SW)
return (0);
- }
delay(1000);
}
@@ -2873,6 +2876,30 @@
}
static void
+mcx_cmdq_mboxes_pas(struct mcx_dmamem *mxm, int offset, int npages,
+ struct mcx_dmamem *buf)
+{
+ uint64_t *pas;
+ int mbox, mbox_pages, i;
+
+ mbox = offset / MCX_CMDQ_MAILBOX_DATASIZE;
+ offset %= MCX_CMDQ_MAILBOX_DATASIZE;
+
+ pas = mcx_cq_mbox_data(mcx_cq_mbox(mxm, mbox));
+ pas += (offset / sizeof(*pas));
+ mbox_pages = (MCX_CMDQ_MAILBOX_DATASIZE - offset) / sizeof(*pas);
+ for (i = 0; i < npages; i++) {
+ if (i == mbox_pages) {
+ mbox++;
+ pas = mcx_cq_mbox_data(mcx_cq_mbox(mxm, mbox));
+ mbox_pages += MCX_CMDQ_MAILBOX_DATASIZE / sizeof(*pas);
+ }
+ *pas = htobe64(MCX_DMA_DVA(buf) + (i * MCX_PAGE_SIZE));
+ pas++;
+ }
+}
+
+static void
mcx_cmdq_mboxes_copyout(struct mcx_dmamem *mxm, int nmb, void *b, size_t len)
{
uint8_t *buf = b;
@@ -3650,7 +3677,7 @@
return (-1);
}
- sc->sc_uar = be32toh(out->cmd_uar);
+ sc->sc_uar = mcx_get_id(out->cmd_uar);
return (0);
}
@@ -3709,11 +3736,7 @@
(1ull << MCX_EVENT_TYPE_PAGE_REQUEST));
/* physical addresses follow the mailbox in data */
- pas = (uint64_t *)(mbin + 1);
- for (i = 0; i < npages; i++) {
- pas[i] = htobe64(MCX_DMA_DVA(&sc->sc_eq_mem) +
- (i * MCX_PAGE_SIZE));
- }
+ mcx_cmdq_mboxes_pas(&mxm, sizeof(*mbin), npages, &sc->sc_eq_mem);
mcx_cmdq_mboxes_sign(&mxm, howmany(insize, MCX_CMDQ_MAILBOX_DATASIZE));
mcx_cmdq_post(sc, cqe, 0);
@@ -3735,7 +3758,7 @@
goto free;
}
- sc->sc_eqn = be32toh(out->cmd_eqn);
+ sc->sc_eqn = mcx_get_id(out->cmd_eqn);
mcx_arm_eq(sc);
free:
mcx_dmamem_free(sc, &mxm);
@@ -3775,7 +3798,7 @@
return (-1);
}
- sc->sc_pd = be32toh(out->cmd_pd);
+ sc->sc_pd = mcx_get_id(out->cmd_pd);
return (0);
}
@@ -3813,7 +3836,7 @@
return (-1);
}
- sc->sc_tdomain = be32toh(out->cmd_tdomain);
+ sc->sc_tdomain = mcx_get_id(out->cmd_tdomain);
return (0);
}
@@ -4002,10 +4025,7 @@
MCX_CQ_DOORBELL_OFFSET + (MCX_CQ_DOORBELL_SIZE * sc->sc_num_cq));
/* physical addresses follow the mailbox in data */
- pas = (uint64_t *)(mbin + 1);
- for (i = 0; i < npages; i++) {
- pas[i] = htobe64(MCX_DMA_DVA(&cq->cq_mem) + (i * MCX_PAGE_SIZE));
- }
+ mcx_cmdq_mboxes_pas(&mxm, sizeof(*mbin), npages, &cq->cq_mem);
mcx_cmdq_post(sc, cmde, 0);
error = mcx_cmdq_poll(sc, cmde, 1000);
@@ -4026,7 +4046,7 @@
goto free;
}
- cq->cq_n = be32toh(out->cmd_cqn);
+ cq->cq_n = mcx_get_id(out->cmd_cqn);
cq->cq_cons = 0;
cq->cq_count = 0;
cq->cq_doorbell = (void *)((uint8_t *)MCX_DMA_KVA(&sc->sc_doorbell_mem) +
@@ -4093,7 +4113,7 @@
int error;
uint64_t *pas;
uint8_t *doorbell;
- int insize, npages, paslen, i, token;
+ int insize, npages, paslen, token;
npages = howmany((1 << MCX_LOG_RQ_SIZE) * sizeof(struct mcx_rq_entry),
MCX_PAGE_SIZE);
@@ -4133,11 +4153,7 @@
mbin->rq_wq.wq_log_size = MCX_LOG_RQ_SIZE;
/* physical addresses follow the mailbox in data */
- pas = (uint64_t *)(mbin + 1);
- for (i = 0; i < npages; i++) {
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