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[src/trunk]: src/sys/arch/x86/include Add MCOMMIT instruction.
details: https://anonhg.NetBSD.org/src/rev/f1d26483f37d
branches: trunk
changeset: 965268:f1d26483f37d
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Mon Sep 09 05:28:32 2019 +0000
description:
Add MCOMMIT instruction.
diffstat:
sys/arch/x86/include/specialreg.h | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diffs (26 lines):
diff -r 733d8f8e5aa3 -r f1d26483f37d sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Mon Sep 09 01:22:24 2019 +0000
+++ b/sys/arch/x86/include/specialreg.h Mon Sep 09 05:28:32 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.151 2019/08/30 13:11:28 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.152 2019/09/09 05:28:32 msaitoh Exp $ */
/*
* Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
@@ -725,6 +725,7 @@
#define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */
#define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */
#define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */
+#define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */
#define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */
#define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */
#define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */
@@ -739,7 +740,7 @@
#define CPUID_CAPEX_FLAGS "\20" \
"\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \
"\5RDPRU" "\7B6" \
- "\11B8" "\12WBNOINVD" "\12B10" \
+ "\11MCOMMIT" "\12WBNOINVD" "\12B10" \
"\15IBPB" "\16B13" "\17IBRS" "\20STIBP" \
"\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \
"\31SSBD" "\32VIRT_SSBD" "\33SSB_NO"
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