[src/trunk]: src/sys/arch/arm/sunxi Add support for A64 I2S clocks.

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/753ff0e11f3d
branches:  trunk
changeset: 966831:753ff0e11f3d
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun Nov 17 17:33:17 2019 +0000

description:
Add support for A64 I2S clocks.

diffstat:

 sys/arch/arm/sunxi/sun50i_a64_ccu.c |  28 +++++++++++++++++++++++++-
 sys/arch/arm/sunxi/sunxi_ccu_div.c  |  38 ++++++++++++++++++++++++++++++++++--
 2 files changed, 61 insertions(+), 5 deletions(-)

diffs (129 lines):

diff -r 4f4ccf1841ba -r 753ff0e11f3d sys/arch/arm/sunxi/sun50i_a64_ccu.c
--- a/sys/arch/arm/sunxi/sun50i_a64_ccu.c       Sun Nov 17 16:52:29 2019 +0000
+++ b/sys/arch/arm/sunxi/sun50i_a64_ccu.c       Sun Nov 17 17:33:17 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sun50i_a64_ccu.c,v 1.13 2019/07/01 21:06:47 jmcneill Exp $ */
+/* $NetBSD: sun50i_a64_ccu.c,v 1.14 2019/11/17 17:33:17 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -28,7 +28,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.13 2019/07/01 21:06:47 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.14 2019/11/17 17:33:17 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -60,6 +60,9 @@
 #define        SDMMC0_CLK_REG          0x088
 #define        SDMMC1_CLK_REG          0x08c
 #define        SDMMC2_CLK_REG          0x090
+#define        I2SPCM0_CLK_REG         0x0b0
+#define        I2SPCM1_CLK_REG         0x0b4
+#define        I2SPCM2_CLK_REG         0x0b8
 #define        USBPHY_CFG_REG          0x0cc
 #define        DRAM_CFG_REG            0x0f4
 #define        MBUS_RST_REG            0x0fc
@@ -154,6 +157,7 @@
 static const char *ths_parents[] = { "hosc", NULL, NULL, NULL };
 static const char *de_parents[] = { "pll_periph0_2x", "pll_de" };
 static const char *hdmi_parents[] = { "pll_video0", "pll_video1" };
+static const char *i2s_parents[] = { "pll_audio_8x", "pll_audio_4x", "pll_audio_2x", "pll_audio" };
 static const char *tcon1_parents[] = { "pll_video0", NULL, "pll_video1", NULL };
 static const char *gpu_parents[] = { "pll_gpu" };
 
@@ -407,6 +411,26 @@
        SUNXI_CCU_GATE(A64_CLK_HDMI_DDC, "hdmi-ddc", "hosc",
            HDMI_SLOW_CLK_REG, 31),
 
+       SUNXI_CCU_DIV_GATE(A64_CLK_I2S0, "i2s0", i2s_parents,
+           I2SPCM0_CLK_REG,    /* reg */
+           0,                  /* div */
+           __BITS(17,16),      /* sel */
+           __BIT(31),          /* enable */
+           0),
+       SUNXI_CCU_DIV_GATE(A64_CLK_I2S1, "i2s1", i2s_parents,
+           I2SPCM1_CLK_REG,    /* reg */
+           0,                  /* div */
+           __BITS(17,16),      /* sel */
+           __BIT(31),          /* enable */
+           0),
+       SUNXI_CCU_DIV_GATE(A64_CLK_I2S2, "i2s2", i2s_parents,
+           I2SPCM2_CLK_REG,    /* reg */
+           0,                  /* div */
+           __BITS(17,16),      /* sel */
+           __BIT(31),          /* enable */
+           0),
+
+
        SUNXI_CCU_DIV_GATE(A64_CLK_TCON1, "tcon1", tcon1_parents,
            TCON1_CLK_REG,      /* reg */
            __BITS(3,0),        /* div */
diff -r 4f4ccf1841ba -r 753ff0e11f3d sys/arch/arm/sunxi/sunxi_ccu_div.c
--- a/sys/arch/arm/sunxi/sunxi_ccu_div.c        Sun Nov 17 16:52:29 2019 +0000
+++ b/sys/arch/arm/sunxi/sunxi_ccu_div.c        Sun Nov 17 17:33:17 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_ccu_div.c,v 1.5 2018/03/19 16:19:17 bouyer Exp $ */
+/* $NetBSD: sunxi_ccu_div.c,v 1.6 2019/11/17 17:33:17 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_ccu_div.c,v 1.5 2018/03/19 16:19:17 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_ccu_div.c,v 1.6 2019/11/17 17:33:17 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -98,6 +98,38 @@
        return rate / ratio;
 }
 
+static int
+sunxi_ccu_div_select_parent(struct sunxi_ccu_softc *sc,
+    struct sunxi_ccu_clk *clk, u_int new_rate)
+{
+       struct sunxi_ccu_div *div = &clk->u.div;
+       struct sunxi_ccu_clk *clk_parent;
+       struct clk *best_parent;
+       u_int index, best_diff;
+       const char *pname;
+
+       best_parent = NULL;
+       best_diff = ~0u;
+       for (index = 0; index < div->nparents; index++) {
+               pname = div->parents[index];
+               if (pname == NULL)
+                       continue;
+               clk_parent = sunxi_ccu_clock_find(sc, pname);
+               if (clk_parent == NULL)
+                       continue;
+               const u_int rate = clk_get_rate(&clk_parent->base);
+               const u_int diff = abs((int)rate - (int)new_rate);
+               if (diff < best_diff) {
+                       best_diff = diff;
+                       best_parent = &clk_parent->base;
+               }
+       }
+       if (best_diff == ~0u)
+               return EINVAL;
+
+       return clk_set_parent(&clk->base, best_parent);
+}
+
 int
 sunxi_ccu_div_set_rate(struct sunxi_ccu_softc *sc,
     struct sunxi_ccu_clk *clk, u_int new_rate)
@@ -119,7 +151,7 @@
                if ((div->flags & SUNXI_CCU_DIV_SET_RATE_PARENT) != 0)
                        return clk_set_rate(clkp_parent, new_rate);
                else
-                       return ENXIO;
+                       return sunxi_ccu_div_select_parent(sc, clk, new_rate);
        }
 
        val = CCU_READ(sc, div->reg);