[src/trunk]: src/sys/dev/ic Use actual hw mode, not proposed mode.

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a946d9aea9ec
branches:  trunk
changeset: 966958:a946d9aea9ec
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sat Nov 23 20:27:39 2019 +0000

description:
Use actual hw mode, not proposed mode.

diffstat:

 sys/arch/arm/sunxi/sunxi_lcdc.c |  47 ++++++++++++++++++++--------------------
 sys/dev/ic/dw_hdmi.c            |  20 ++++++++--------
 2 files changed, 33 insertions(+), 34 deletions(-)

diffs (141 lines):

diff -r 90e4cf1df4e9 -r a946d9aea9ec sys/arch/arm/sunxi/sunxi_lcdc.c
--- a/sys/arch/arm/sunxi/sunxi_lcdc.c   Sat Nov 23 20:24:12 2019 +0000
+++ b/sys/arch/arm/sunxi/sunxi_lcdc.c   Sat Nov 23 20:27:39 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sunxi_lcdc.c,v 1.6 2019/07/06 00:23:38 jmcneill Exp $ */
+/* $NetBSD: sunxi_lcdc.c,v 1.7 2019/11/23 20:28:04 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2019 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_lcdc.c,v 1.6 2019/07/06 00:23:38 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_lcdc.c,v 1.7 2019/11/23 20:28:04 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -81,7 +81,7 @@
 #define        TCON1_CTL_REG           0x090
 #define         TCON1_CTL_TCON1_EN                     __BIT(31)
 #define         TCON1_CTL_START_DELAY                  __BITS(8,4)
-#define         TCON1_CTL_TCON1_SRC_SEL                __BIT(1)
+#define         TCON1_CTL_TCON1_SRC_SEL                __BITS(1,0)
 #define        TCON1_BASIC0_REG        0x094
 #define        TCON1_BASIC1_REG        0x098
 #define        TCON1_BASIC2_REG        0x09c
@@ -185,6 +185,7 @@
 
        val = TCON_READ(sc, TCON_GCTL_REG);
        val |= TCON_GCTL_TCON_EN;
+       val &= ~TCON_GCTL_IO_MAP_SEL;
        TCON_WRITE(sc, TCON_GCTL_REG, val);
 
        TCON_WRITE(sc, TCON0_IO_TRI_REG, 0);
@@ -215,20 +216,20 @@
        int error;
 
        const u_int interlace_p = (mode->flags & DRM_MODE_FLAG_INTERLACE) != 0;
-       const u_int hspw = mode->hsync_end - mode->hsync_start;
-       const u_int hbp = mode->htotal - mode->hsync_start;
-       const u_int vspw = mode->vsync_end - mode->vsync_start;
-       const u_int vbp = mode->vtotal - mode->vsync_start;
-       const u_int vblank_len = (mode->vtotal - mode->vdisplay) >> interlace_p;
+       const u_int hspw = mode->crtc_hsync_end - mode->crtc_hsync_start;
+       const u_int hbp = mode->crtc_htotal - mode->crtc_hsync_start;
+       const u_int vspw = mode->crtc_vsync_end - mode->crtc_vsync_start;
+       const u_int vbp = mode->crtc_vtotal - mode->crtc_vsync_start;
+       const u_int vblank_len = (mode->crtc_vtotal - mode->crtc_vdisplay) >> interlace_p;
        const u_int start_delay = uimin(vblank_len, 30);
 
        val = TCON0_CTL_TCON0_EN |
              __SHIFTIN(start_delay, TCON0_CTL_START_DELAY);
        TCON_WRITE(sc, TCON0_CTL_REG, val);
 
-       TCON_WRITE(sc, TCON0_BASIC0_REG, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
-       TCON_WRITE(sc, TCON0_BASIC1_REG, ((mode->htotal - 1) << 16) | (hbp - 1));
-       TCON_WRITE(sc, TCON0_BASIC2_REG, ((mode->vtotal * 2) << 16) | (vbp - 1));
+       TCON_WRITE(sc, TCON0_BASIC0_REG, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
+       TCON_WRITE(sc, TCON0_BASIC1_REG, ((mode->crtc_htotal - 1) << 16) | (hbp - 1));
+       TCON_WRITE(sc, TCON0_BASIC2_REG, ((mode->crtc_vtotal * 2) << 16) | (vbp - 1));
        TCON_WRITE(sc, TCON0_BASIC3_REG, ((hspw - 1) << 16) | (vspw - 1));
 
        val = TCON_READ(sc, TCON0_IO_POL_REG);
@@ -268,24 +269,22 @@
        int error;
 
        const u_int interlace_p = (mode->flags & DRM_MODE_FLAG_INTERLACE) != 0;
-       const u_int hspw = mode->hsync_end - mode->hsync_start;
-       const u_int hbp = mode->htotal - mode->hsync_start;
-       const u_int vspw = mode->vsync_end - mode->vsync_start;
-       const u_int vbp = mode->vtotal - mode->vsync_start;
-       const u_int vblank_len =
-           ((mode->vtotal << interlace_p) >> 1) - mode->vdisplay - 2;
-       const u_int start_delay =
-           vblank_len >= 32 ? 30 : vblank_len - 2;
+       const u_int hspw = mode->crtc_hsync_end - mode->crtc_hsync_start;
+       const u_int hbp = mode->crtc_htotal - mode->crtc_hsync_start;
+       const u_int vspw = mode->crtc_vsync_end - mode->crtc_vsync_start;
+       const u_int vbp = mode->crtc_vtotal - mode->crtc_vsync_start;
+       const u_int vblank_len = ((mode->crtc_vtotal - mode->crtc_vdisplay) >> interlace_p) - 2;
+       const u_int start_delay = uimin(vblank_len, 30);
 
        val = TCON1_CTL_TCON1_EN |
              __SHIFTIN(start_delay, TCON1_CTL_START_DELAY);
        TCON_WRITE(sc, TCON1_CTL_REG, val);
 
-       TCON_WRITE(sc, TCON1_BASIC0_REG, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
-       TCON_WRITE(sc, TCON1_BASIC1_REG, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
-       TCON_WRITE(sc, TCON1_BASIC2_REG, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
-       TCON_WRITE(sc, TCON1_BASIC3_REG, ((mode->htotal - 1) << 16) | (hbp - 1));
-       TCON_WRITE(sc, TCON1_BASIC4_REG, ((mode->vtotal * 2) << 16) | (vbp - 1));
+       TCON_WRITE(sc, TCON1_BASIC0_REG, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
+       TCON_WRITE(sc, TCON1_BASIC1_REG, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
+       TCON_WRITE(sc, TCON1_BASIC2_REG, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1));
+       TCON_WRITE(sc, TCON1_BASIC3_REG, ((mode->crtc_htotal - 1) << 16) | (hbp - 1));
+       TCON_WRITE(sc, TCON1_BASIC4_REG, ((mode->crtc_vtotal * 2) << 16) | (vbp - 1));
        TCON_WRITE(sc, TCON1_BASIC5_REG, ((hspw - 1) << 16) | (vspw - 1));
 
        TCON_WRITE(sc, TCON_GINT1_REG,
diff -r 90e4cf1df4e9 -r a946d9aea9ec sys/dev/ic/dw_hdmi.c
--- a/sys/dev/ic/dw_hdmi.c      Sat Nov 23 20:24:12 2019 +0000
+++ b/sys/dev/ic/dw_hdmi.c      Sat Nov 23 20:27:39 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dw_hdmi.c,v 1.5 2019/11/23 12:28:44 jmcneill Exp $ */
+/* $NetBSD: dw_hdmi.c,v 1.6 2019/11/23 20:27:39 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2019 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dw_hdmi.c,v 1.5 2019/11/23 12:28:44 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dw_hdmi.c,v 1.6 2019/11/23 20:27:39 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -429,14 +429,14 @@
        uint8_t val;
 
        const uint8_t vic = drm_match_cea_mode(mode);
-       const uint16_t inhactiv = mode->hdisplay;
-       const uint16_t inhblank = mode->htotal - mode->hdisplay;
-       const uint16_t invactiv = mode->vdisplay;
-       const uint8_t invblank = mode->vtotal - mode->vdisplay;
-       const uint16_t hsyncindelay = mode->hsync_start - mode->hdisplay;
-       const uint16_t hsyncinwidth = mode->hsync_end - mode->hsync_start;
-       const uint8_t vsyncindelay = mode->vsync_start - mode->vdisplay;
-       const uint8_t vsyncinwidth = mode->vsync_end - mode->vsync_start;
+       const uint16_t inhactiv = mode->crtc_hdisplay;
+       const uint16_t inhblank = mode->crtc_htotal - mode->crtc_hdisplay;
+       const uint16_t invactiv = mode->crtc_vdisplay;
+       const uint8_t invblank = mode->crtc_vtotal - mode->crtc_vdisplay;
+       const uint16_t hsyncindelay = mode->crtc_hsync_start - mode->crtc_hdisplay;
+       const uint16_t hsyncinwidth = mode->crtc_hsync_end - mode->crtc_hsync_start;
+       const uint8_t vsyncindelay = mode->crtc_vsync_start - mode->crtc_vdisplay;
+       const uint8_t vsyncinwidth = mode->crtc_vsync_end - mode->crtc_vsync_start;
 
        /* Input video configuration for frame composer */
        val = HDMI_FC_INVIDCONF_DE_IN_POLARITY;