[src/trunk]: src/sys/arch/aarch64 Enable early write acknowledge for device m...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/44746639cf54
branches:  trunk
changeset: 967928:44746639cf54
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Fri Dec 27 18:56:47 2019 +0000

description:
Enable early write acknowledge for device memory mappings.

diffstat:

 sys/arch/aarch64/aarch64/genassym.cf |   3 ++-
 sys/arch/aarch64/aarch64/locore.S    |  11 ++++++++---
 sys/arch/aarch64/aarch64/pmap.c      |   6 +++---
 sys/arch/aarch64/conf/files.aarch64  |   3 ++-
 sys/arch/aarch64/include/armreg.h    |   3 ++-
 sys/arch/aarch64/include/pmap.h      |   4 ++--
 6 files changed, 19 insertions(+), 11 deletions(-)

diffs (127 lines):

diff -r c61c991ffb5e -r 44746639cf54 sys/arch/aarch64/aarch64/genassym.cf
--- a/sys/arch/aarch64/aarch64/genassym.cf      Fri Dec 27 15:49:20 2019 +0000
+++ b/sys/arch/aarch64/aarch64/genassym.cf      Fri Dec 27 18:56:47 2019 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.15 2019/11/24 11:23:16 skrll Exp $
+# $NetBSD: genassym.cf,v 1.16 2019/12/27 18:56:47 jmcneill Exp $
 #-
 # Copyright (c) 2014 The NetBSD Foundation, Inc.
 # All rights reserved.
@@ -336,6 +336,7 @@
 define MAIR_ATTR2              MAIR_ATTR2
 define MAIR_ATTR3              MAIR_ATTR3
 define MAIR_DEVICE_nGnRnE      MAIR_DEVICE_nGnRnE
+define MAIR_DEVICE_nGnRE       MAIR_DEVICE_nGnRE
 define MAIR_NORMAL_NC          MAIR_NORMAL_NC
 define MAIR_NORMAL_WT          MAIR_NORMAL_WT
 define MAIR_NORMAL_WB          MAIR_NORMAL_WB
diff -r c61c991ffb5e -r 44746639cf54 sys/arch/aarch64/aarch64/locore.S
--- a/sys/arch/aarch64/aarch64/locore.S Fri Dec 27 15:49:20 2019 +0000
+++ b/sys/arch/aarch64/aarch64/locore.S Fri Dec 27 18:56:47 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.47 2019/12/26 08:48:53 skrll Exp $        */
+/*     $NetBSD: locore.S,v 1.48 2019/12/27 18:56:47 jmcneill Exp $     */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -38,8 +38,13 @@
 #include <aarch64/hypervisor.h>
 #include "assym.h"
 
-RCSID("$NetBSD: locore.S,v 1.47 2019/12/26 08:48:53 skrll Exp $")
+RCSID("$NetBSD: locore.S,v 1.48 2019/12/27 18:56:47 jmcneill Exp $")
 
+#ifdef AARCH64_DEVICE_MEM_STRICTLY_ORDERED
+#define        MAIR_DEVICE_MEM         MAIR_DEVICE_nGnRnE
+#else
+#define        MAIR_DEVICE_MEM         MAIR_DEVICE_nGnRE
+#endif
 
 /*#define DEBUG_LOCORE                 /* debug print */
 /*#define DEBUG_LOCORE_PRINT_LOCK      /* avoid mixing AP's output */
@@ -948,7 +953,7 @@
            __SHIFTIN(MAIR_NORMAL_WB, MAIR_ATTR0) |     \
            __SHIFTIN(MAIR_NORMAL_NC, MAIR_ATTR1) |     \
            __SHIFTIN(MAIR_NORMAL_WT, MAIR_ATTR2) |     \
-           __SHIFTIN(MAIR_DEVICE_nGnRnE, MAIR_ATTR3))
+           __SHIFTIN(MAIR_DEVICE_MEM, MAIR_ATTR3))
 
 #define VIRT_BIT       48
 
diff -r c61c991ffb5e -r 44746639cf54 sys/arch/aarch64/aarch64/pmap.c
--- a/sys/arch/aarch64/aarch64/pmap.c   Fri Dec 27 15:49:20 2019 +0000
+++ b/sys/arch/aarch64/aarch64/pmap.c   Fri Dec 27 18:56:47 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.56 2019/12/19 07:44:56 skrll Exp $  */
+/*     $NetBSD: pmap.c,v 1.57 2019/12/27 18:56:47 jmcneill Exp $       */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.56 2019/12/19 07:44:56 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.57 2019/12/27 18:56:47 jmcneill Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -953,7 +953,7 @@
 
        switch (flags & (PMAP_CACHE_MASK|PMAP_DEV)) {
        case PMAP_DEV ... PMAP_DEV | PMAP_CACHE_MASK:
-               pte |= LX_BLKPAG_ATTR_DEVICE_MEM;       /* nGnRnE */
+               pte |= LX_BLKPAG_ATTR_DEVICE_MEM;       /* Device-nGnRE */
                break;
        case PMAP_NOCACHE:
        case PMAP_NOCACHE_OVR:
diff -r c61c991ffb5e -r 44746639cf54 sys/arch/aarch64/conf/files.aarch64
--- a/sys/arch/aarch64/conf/files.aarch64       Fri Dec 27 15:49:20 2019 +0000
+++ b/sys/arch/aarch64/conf/files.aarch64       Fri Dec 27 18:56:47 2019 +0000
@@ -1,9 +1,10 @@
-#      $NetBSD: files.aarch64,v 1.14 2019/11/20 19:37:51 pgoyette Exp $
+#      $NetBSD: files.aarch64,v 1.15 2019/12/27 18:56:47 jmcneill Exp $
 
 defflag opt_cpuoptions.h       AARCH64_ALIGNMENT_CHECK
 defflag opt_cpuoptions.h       AARCH64_EL0_STACK_ALIGNMENT_CHECK
 defflag opt_cpuoptions.h       AARCH64_EL1_STACK_ALIGNMENT_CHECK
 defflag opt_cpuoptions.h       AARCH64_HAVE_L2CTLR
+defflag opt_cpuoptions.h       AARCH64_DEVICE_MEM_STRICTLY_ORDERED
 
 defflag        opt_cputypes.h          CPU_ARMV8
 defflag        opt_cputypes.h          CPU_CORTEX: CPU_ARMV8
diff -r c61c991ffb5e -r 44746639cf54 sys/arch/aarch64/include/armreg.h
--- a/sys/arch/aarch64/include/armreg.h Fri Dec 27 15:49:20 2019 +0000
+++ b/sys/arch/aarch64/include/armreg.h Fri Dec 27 18:56:47 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.28 2019/09/15 15:16:30 tnn Exp $ */
+/* $NetBSD: armreg.h,v 1.29 2019/12/27 18:56:47 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -523,6 +523,7 @@
 #define        MAIR_ATTR6               __BITS(55,48)
 #define        MAIR_ATTR7               __BITS(63,56)
 #define        MAIR_DEVICE_nGnRnE       0x00   // NoGathering,NoReordering,NoEarlyWriteAck.
+#define        MAIR_DEVICE_nGnRE        0x04   // NoGathering,NoReordering,EarlyWriteAck.
 #define        MAIR_NORMAL_NC           0x44
 #define        MAIR_NORMAL_WT           0xbb
 #define        MAIR_NORMAL_WB           0xff
diff -r c61c991ffb5e -r 44746639cf54 sys/arch/aarch64/include/pmap.h
--- a/sys/arch/aarch64/include/pmap.h   Fri Dec 27 15:49:20 2019 +0000
+++ b/sys/arch/aarch64/include/pmap.h   Fri Dec 27 18:56:47 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.26 2019/10/29 20:01:22 maya Exp $ */
+/* $NetBSD: pmap.h,v 1.27 2019/12/27 18:56:47 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -240,7 +240,7 @@
         *  WriteBack      - write back cache
         *  WriteThru      - wite through cache
         *  NoCache        - no cache
-        *  Device(nGnRnE) - no Gathering, no Reordering, no Early write ack
+        *  Device(nGnRE)  - no Gathering, no Reordering, Early write ack
         *
         * but pmap has PMAP_{NOCACHE,WRITE_COMBINE,WRITE_BACK} flags.
         */