[src/trunk]: src/sys/arch/aarch64/aarch64 Flush the cache and disable TTBR0 t...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/f29194c161d2
branches:  trunk
changeset: 967972:f29194c161d2
user:      skrll <skrll%NetBSD.org@localhost>
date:      Mon Dec 30 15:54:55 2019 +0000

description:
Flush the cache and disable TTBR0 translations once we're done with
them in cpu_kernel_vm_init

The Cortex A72s in RPI4 need the cache flush for some reason.

diffstat:

 sys/arch/aarch64/aarch64/aarch64_machdep.c |  11 +++++++++--
 1 files changed, 9 insertions(+), 2 deletions(-)

diffs (32 lines):

diff -r d1af799bcd85 -r f29194c161d2 sys/arch/aarch64/aarch64/aarch64_machdep.c
--- a/sys/arch/aarch64/aarch64/aarch64_machdep.c        Mon Dec 30 15:42:39 2019 +0000
+++ b/sys/arch/aarch64/aarch64/aarch64_machdep.c        Mon Dec 30 15:54:55 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: aarch64_machdep.c,v 1.35 2019/12/18 21:45:43 riastradh Exp $ */
+/* $NetBSD: aarch64_machdep.c,v 1.36 2019/12/30 15:54:55 skrll Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.35 2019/12/18 21:45:43 riastradh Exp $");
+__KERNEL_RCSID(1, "$NetBSD: aarch64_machdep.c,v 1.36 2019/12/30 15:54:55 skrll Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -205,6 +205,13 @@
                        left -= mapsize;
                }
        }
+       aarch64_dcache_wbinv_all();
+
+       /* Disable translation table walks using TTBR0 */
+       uint64_t tcr = reg_tcr_el1_read();
+       reg_tcr_el1_write(tcr | TCR_EPD0);
+       __asm __volatile("isb" ::: "memory");
+
        aarch64_tlbi_all();
 
        /*