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[src/trunk]: src/sys/dev/nvmm/x86 Improve emulation of MSR_IA32_ARCH_CAPABILI...
details: https://anonhg.NetBSD.org/src/rev/982c6c7f50f2
branches: trunk
changeset: 974797:982c6c7f50f2
user: maxv <maxv%NetBSD.org@localhost>
date: Tue Aug 11 15:27:46 2020 +0000
description:
Improve emulation of MSR_IA32_ARCH_CAPABILITIES: publish only the *_NO
bits. Initially they were the only ones there, but Intel then added other
bits we aren't interested in, and they must be filtered out.
diffstat:
sys/dev/nvmm/x86/nvmm_x86_vmx.c | 24 ++++++++++++++++++++----
1 files changed, 20 insertions(+), 4 deletions(-)
diffs (52 lines):
diff -r 5416720e5756 -r 982c6c7f50f2 sys/dev/nvmm/x86/nvmm_x86_vmx.c
--- a/sys/dev/nvmm/x86/nvmm_x86_vmx.c Tue Aug 11 15:23:10 2020 +0000
+++ b/sys/dev/nvmm/x86/nvmm_x86_vmx.c Tue Aug 11 15:27:46 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmm_x86_vmx.c,v 1.67 2020/08/05 15:20:09 maxv Exp $ */
+/* $NetBSD: nvmm_x86_vmx.c,v 1.68 2020/08/11 15:27:46 maxv Exp $ */
/*
* Copyright (c) 2018-2020 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_vmx.c,v 1.67 2020/08/05 15:20:09 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_vmx.c,v 1.68 2020/08/11 15:27:46 maxv Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -1734,6 +1734,24 @@
cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32);
goto handled;
}
+ if (exit->u.rdmsr.msr == MSR_IA32_ARCH_CAPABILITIES) {
+ u_int descs[4];
+ if (cpuid_level < 7) {
+ goto error;
+ }
+ x86_cpuid(7, descs);
+ if (!(descs[3] & CPUID_SEF_ARCH_CAP)) {
+ goto error;
+ }
+ val = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
+ val &= (IA32_ARCH_RDCL_NO |
+ IA32_ARCH_SSB_NO |
+ IA32_ARCH_MDS_NO |
+ IA32_ARCH_TAA_NO);
+ cpudata->gprs[NVMM_X64_GPR_RAX] = (val & 0xFFFFFFFF);
+ cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32);
+ goto handled;
+ }
for (i = 0; i < __arraycount(msr_ignore_list); i++) {
if (msr_ignore_list[i] != exit->u.rdmsr.msr)
continue;
@@ -2765,8 +2783,6 @@
vmx_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true);
vmx_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true);
vmx_vcpu_msr_allow(cpudata->msrbm, MSR_TSC, true, false);
- vmx_vcpu_msr_allow(cpudata->msrbm, MSR_IA32_ARCH_CAPABILITIES,
- true, false);
vmx_vmwrite(VMCS_MSR_BITMAP, (uint64_t)cpudata->msrbm_pa);
/*
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