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[src/trunk]: src/sys/dev/pci - Use the 64-bit PCI DMA tag if available.



details:   https://anonhg.NetBSD.org/src/rev/2f69cbeb18c7
branches:  trunk
changeset: 969764:2f69cbeb18c7
user:      thorpej <thorpej%NetBSD.org@localhost>
date:      Sun Mar 01 02:51:42 2020 +0000

description:
- Use the 64-bit PCI DMA tag if available.
- In age_dma_alloc(), ensure that all of the control data end up in the
  same 4GB segment, because the hardware requires this.

diffstat:

 sys/dev/pci/if_age.c |  35 ++++++++++++++++++++++++++++++++---
 1 files changed, 32 insertions(+), 3 deletions(-)

diffs (66 lines):

diff -r 2841a24c0642 -r 2f69cbeb18c7 sys/dev/pci/if_age.c
--- a/sys/dev/pci/if_age.c      Sun Mar 01 02:45:04 2020 +0000
+++ b/sys/dev/pci/if_age.c      Sun Mar 01 02:51:42 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_age.c,v 1.68 2020/03/01 02:28:14 thorpej Exp $ */
+/*     $NetBSD: if_age.c,v 1.69 2020/03/01 02:51:42 thorpej Exp $ */
 /*     $OpenBSD: if_age.c,v 1.1 2009/01/16 05:00:34 kevlo Exp $        */
 
 /*-
@@ -31,7 +31,7 @@
 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.68 2020/03/01 02:28:14 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_age.c,v 1.69 2020/03/01 02:51:42 thorpej Exp $");
 
 #include "vlan.h"
 
@@ -152,10 +152,14 @@
        aprint_normal(": Attansic/Atheros L1 Gigabit Ethernet\n");
 
        sc->sc_dev = self;
-       sc->sc_dmat = pa->pa_dmat;
        sc->sc_pct = pa->pa_pc;
        sc->sc_pcitag = pa->pa_tag;
 
+       if (pci_dma64_available(pa))
+               sc->sc_dmat = pa->pa_dmat64;
+       else
+               sc->sc_dmat = pa->pa_dmat;
+
        /*
         * Allocate IO memory
         */
@@ -901,6 +905,31 @@
        sc->age_rdata.age_smb_block_paddr =
            sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr;
 
+       /*
+        * All of the memory we allocated above needs to be within
+        * the same 4GB segment.  Make sure this is so.
+        *
+        * XXX We don't care WHAT 4GB segment they're in, just that
+        * XXX they're all in the same one.  Need some bus_dma API
+        * XXX help to make this easier to enforce when we actually
+        * XXX perform the allocation.
+        */
+       if (! (AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr) ==
+              AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)
+
+           && AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr) ==
+              AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)
+
+           && AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr) ==
+              AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)
+
+           && AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr) ==
+              AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) {
+               aprint_error_dev(sc->sc_dev,
+                   "control data allocation constraints failed\n");
+               return ENOBUFS;
+       }
+
        /* Create DMA maps for Tx buffers. */
        for (i = 0; i < AGE_TX_RING_CNT; i++) {
                txd = &sc->age_cdata.age_txdesc[i];



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