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[src/trunk]: src/sys/arch/shark Driver for the I2C bus used for RAM serial pr...
details: https://anonhg.NetBSD.org/src/rev/de2a661df681
branches: trunk
changeset: 982867:de2a661df681
user: thorpej <thorpej%NetBSD.org@localhost>
date: Fri Apr 30 02:24:05 2021 +0000
description:
Driver for the I2C bus used for RAM serial presence detection. This
I2C interface is implemented by bit-banging a couple of GPIO pins on
the Sequoia core logic used in the Shark.
Heavy lifting by Julian Coleman, and minor tweaks and a different
autoconfiguration scheme by me.
diffstat:
sys/arch/shark/conf/GENERIC | 12 +-
sys/arch/shark/conf/files.shark | 7 +-
sys/arch/shark/shark/shark_iic.c | 291 +++++++++++++++++++++++++++++++++++++++
3 files changed, 307 insertions(+), 3 deletions(-)
diffs (truncated from 349 to 300 lines):
diff -r 04e082cceb21 -r de2a661df681 sys/arch/shark/conf/GENERIC
--- a/sys/arch/shark/conf/GENERIC Fri Apr 30 02:13:15 2021 +0000
+++ b/sys/arch/shark/conf/GENERIC Fri Apr 30 02:24:05 2021 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.139 2021/04/30 02:11:37 thorpej Exp $
+# $NetBSD: GENERIC,v 1.140 2021/04/30 02:24:05 thorpej Exp $
#
# Generic Shark configuration.
#
@@ -7,7 +7,7 @@
options INCLUDE_CONFIG_FILE # embed config file in kernel binary
-#ident "GENERIC-$Revision: 1.139 $"
+#ident "GENERIC-$Revision: 1.140 $"
# estimated number of users
maxusers 32
@@ -211,6 +211,14 @@
sequoia* at ofbus?
ofisa* at sequoia?
+# Shark I2C interface
+sharkiic* at sequoia?
+iic* at sharkiic?
+
+# Only 2 DIMM slots in a Shark.
+spdmem* at iic? addr 0x50
+spdmem* at iic? addr 0x51
+
# IDE/ATA disk
wdc* at ofisa?
atabus* at wdc? channel ?
diff -r 04e082cceb21 -r de2a661df681 sys/arch/shark/conf/files.shark
--- a/sys/arch/shark/conf/files.shark Fri Apr 30 02:13:15 2021 +0000
+++ b/sys/arch/shark/conf/files.shark Fri Apr 30 02:24:05 2021 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.shark,v 1.23 2021/04/30 02:11:37 thorpej Exp $
+# $NetBSD: files.shark,v 1.24 2021/04/30 02:24:05 thorpej Exp $
#
# First try for arm-specific configuration info
#
@@ -60,6 +60,11 @@
device sequoia { }: ofisa_subclass
attach sequoia at ofbus
+# Shark I2C (for DRAM SPD)
+device sharkiic: i2cbus
+attach sharkiic at sequoia
+file arch/shark/shark/shark_iic.c sharkiic
+
# Glue for OFW ISA device attachment
device ofisascr {}
attach ofisascr at ofisa
diff -r 04e082cceb21 -r de2a661df681 sys/arch/shark/shark/shark_iic.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/shark/shark/shark_iic.c Fri Apr 30 02:24:05 2021 +0000
@@ -0,0 +1,291 @@
+/* $NetBSD: shark_iic.c,v 1.1 2021/04/30 02:24:05 thorpej Exp $ */
+
+/*
+ * Copyright (c) 2021 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Julian Coleman.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(0, "$NetBSD: shark_iic.c,v 1.1 2021/04/30 02:24:05 thorpej Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+
+#include <dev/ofw/openfirm.h>
+
+#include <shark/shark/sequoia.h>
+
+#include <dev/i2c/i2cvar.h>
+#include <dev/i2c/i2c_bitbang.h>
+
+#include <arm/cpufunc.h>
+
+/* define registers on sequoia used by pins */
+#define SEQUOIA_1GPIO PMC_GPCR_REG /* reg 0x007 gpio 0-3 */
+#define SEQUOIA_2GPIO SEQ2_OGPIOCR_REG /* reg 0x304 gpio 4.8 */
+
+/* define pins on sequoia that talk to the DIMM I2C bus */
+#define IIC_CLK FOMPCR_M_PCON9
+#define IIC_DATA_IN_DIR GPCR_M_GPIODIR3
+#define IIC_DATA_IN GPCR_M_GPIODATA3
+#define IIC_DATA_OUT_DIR GPIOCR2_M_GPIOBDIR1
+
+/* logical i2c signals */
+#define SHARK_IIC_BIT_SDA 0x01
+#define SHARK_IIC_BIT_SCL 0x02
+#define SHARK_IIC_BIT_OUTPUT 0x04
+#define SHARK_IIC_BIT_INPUT 0x08
+
+struct sharkiic_softc {
+ device_t sc_dev;
+ struct i2c_controller sc_i2c;
+};
+
+/* I2C bitbanging */
+
+static void
+sequoiaBBInit(void)
+{
+ uint16_t seqReg;
+
+ sequoiaLock();
+
+ /*
+ * SCL initialization
+ * - enable pc[9]
+ * - set pin to low (0)
+ */
+ sequoiaRead(SEQR_SEQPSR3_REG, &seqReg);
+ CLR(seqReg, SEQPSR3_M_PC9PINEN);
+ sequoiaWrite(SEQR_SEQPSR3_REG, seqReg);
+ sequoiaRead(PMC_FOMPCR_REG, &seqReg);
+ SET(seqReg, IIC_CLK);
+ sequoiaWrite(PMC_FOMPCR_REG, seqReg);
+
+ /*
+ * SDA (Output) initialization
+ * - set direction to output
+ * - enable GPIO B1 (sets pin to low)
+ */
+ sequoiaRead(PMC_GPIOCR2_REG, &seqReg);
+ SET(seqReg, IIC_DATA_OUT_DIR);
+ sequoiaWrite(PMC_GPIOCR2_REG, seqReg);
+ sequoiaRead(SEQR_SEQPSR2_REG, &seqReg);
+ SET(seqReg, SEQPSR2_M_GPIOB1PINEN);
+ sequoiaWrite(SEQR_SEQPSR2_REG, seqReg);
+
+ /*
+ * SDA (Input) initialization
+ * - enable GPIO
+ * - set direction to input
+ */
+ sequoiaRead(SEQ2_SEQ2PSR_REG, &seqReg);
+ CLR(seqReg, SEQ2PSR_M_GPIOPINEN);
+ sequoiaWrite(SEQ2_SEQ2PSR_REG, seqReg);
+ sequoiaRead(SEQUOIA_1GPIO, &seqReg);
+ CLR(seqReg, IIC_DATA_IN_DIR);
+ sequoiaWrite(SEQUOIA_1GPIO, seqReg);
+
+ sequoiaUnlock();
+}
+
+static void
+sequoiaBBSetBits(uint32_t bits)
+{
+ uint16_t seqRegSDA, seqRegSCL;
+
+ sequoiaLock();
+
+ sequoiaRead(PMC_FOMPCR_REG, &seqRegSCL);
+ sequoiaRead(SEQR_SEQPSR2_REG, &seqRegSDA);
+
+ /*
+ * For SCL and SDA:
+ * - output is the inverse of the desired signal
+ * - the pin enable bit drives the signal
+ */
+ if (bits & SHARK_IIC_BIT_SCL) {
+ CLR(seqRegSCL, IIC_CLK);
+ } else {
+ SET(seqRegSCL, IIC_CLK);
+ }
+
+ if (bits & SHARK_IIC_BIT_SDA) {
+ CLR(seqRegSDA, SEQPSR2_M_GPIOB1PINEN);
+ } else {
+ SET(seqRegSDA, SEQPSR2_M_GPIOB1PINEN);
+ }
+
+ sequoiaWrite(PMC_FOMPCR_REG, seqRegSCL);
+ sequoiaWrite(SEQR_SEQPSR2_REG, seqRegSDA);
+
+ sequoiaUnlock();
+}
+
+static void
+sequoiaBBSetDir(uint32_t dir)
+{
+ uint16_t seqReg;
+
+ sequoiaLock();
+
+ /*
+ * For direction = Input, set SDA (Output) direction to input,
+ * otherwise we'll only read our own signal on SDA (Input)
+ */
+ sequoiaRead(PMC_GPIOCR2_REG, &seqReg);
+ if (dir & SHARK_IIC_BIT_OUTPUT)
+ SET(seqReg, IIC_DATA_OUT_DIR);
+ else
+ CLR(seqReg, IIC_DATA_OUT_DIR);
+ sequoiaWrite(PMC_GPIOCR2_REG, seqReg);
+
+ sequoiaUnlock();
+}
+
+static uint32_t
+sequoiaBBRead(void)
+{
+ uint16_t seqRegSDA, seqRegSCL;
+ uint32_t bits = 0;
+
+ sequoiaLock();
+
+ sequoiaRead(SEQUOIA_1GPIO, &seqRegSDA);
+ sequoiaRead(PMC_FOMPCR_REG, &seqRegSCL);
+
+ sequoiaUnlock();
+
+ if (ISSET(seqRegSDA, IIC_DATA_IN))
+ bits |= SHARK_IIC_BIT_SDA;
+ if (!ISSET(seqRegSCL, IIC_CLK))
+ bits |= SHARK_IIC_BIT_SCL;
+
+ return bits;
+}
+
+static void
+sharkiicbb_set_bits(void *cookie, uint32_t bits)
+{
+ sequoiaBBSetBits(bits);
+}
+
+static void
+sharkiicbb_set_dir(void *cookie, uint32_t dir)
+{
+ sequoiaBBSetDir(dir);
+}
+
+static uint32_t
+sharkiicbb_read(void *cookie)
+{
+ return sequoiaBBRead();
+}
+
+static const struct i2c_bitbang_ops sharkiicbb_ops = {
+ .ibo_set_bits = sharkiicbb_set_bits,
+ .ibo_set_dir = sharkiicbb_set_dir,
+ .ibo_read_bits = sharkiicbb_read,
+ .ibo_bits = {
+ [I2C_BIT_SDA] = SHARK_IIC_BIT_SDA,
+ [I2C_BIT_SCL] = SHARK_IIC_BIT_SCL,
+ [I2C_BIT_OUTPUT] = SHARK_IIC_BIT_OUTPUT,
+ [I2C_BIT_INPUT] = SHARK_IIC_BIT_INPUT,
+ },
+};
+
+/* higher level I2C stuff */
+
+static int
+sharkiic_send_start(void *cookie, int flags)
+{
+ return (i2c_bitbang_send_start(cookie, flags, &sharkiicbb_ops));
+}
+
+static int
+sharkiic_send_stop(void *cookie, int flags)
+{
+ return (i2c_bitbang_send_stop(cookie, flags, &sharkiicbb_ops));
+}
+
+static int
+sharkiic_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
+{
+ return (i2c_bitbang_initiate_xfer(cookie, addr, flags,
+ &sharkiicbb_ops));
+}
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