[src/trunk]: src/sys/arch/aarch64/aarch64 It is enough to make a page accessi...

[ryo <ryo%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/ad9e07efc751
branches:  trunk
changeset: 980346:ad9e07efc751
user:      ryo <ryo%NetBSD.org@localhost>
date:      Mon Feb 01 18:12:11 2021 +0000

description:
It is enough to make a page accessible instead of writable.
same fix as r1.76

diffstat:

 sys/arch/aarch64/aarch64/pmap.c |  15 ++++++---------
 1 files changed, 6 insertions(+), 9 deletions(-)

diffs (43 lines):

diff -r 0c5d25944d7e -r ad9e07efc751 sys/arch/aarch64/aarch64/pmap.c
--- a/sys/arch/aarch64/aarch64/pmap.c   Mon Feb 01 17:50:53 2021 +0000
+++ b/sys/arch/aarch64/aarch64/pmap.c   Mon Feb 01 18:12:11 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.100 2021/01/31 04:51:29 ryo Exp $   */
+/*     $NetBSD: pmap.c,v 1.101 2021/02/01 18:12:11 ryo Exp $   */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.100 2021/01/31 04:51:29 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.101 2021/02/01 18:12:11 ryo Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -960,20 +960,17 @@
                        vaddr_t eob = (va + blocksize) & ~(blocksize - 1);
                        vsize_t len = ulmin(eva, eob) - va;
 
-                       if (l3pte_writable(pte)) {
+                       if (l3pte_readable(pte)) {
                                cpu_icache_sync_range(va, len);
                        } else {
                                /*
-                                * change to writable temporally
+                                * change to accessible temporally
                                 * to do cpu_icache_sync_range()
                                 */
-                               pt_entry_t opte = pte;
-                               pte = pte & ~(LX_BLKPAG_AF|LX_BLKPAG_AP);
-                               pte |= (LX_BLKPAG_AF|LX_BLKPAG_AP_RW);
-                               atomic_swap_64(ptep, pte);
+                               atomic_swap_64(ptep, pte | LX_BLKPAG_AF);
                                AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true);
                                cpu_icache_sync_range(va, len);
-                               atomic_swap_64(ptep, opte);
+                               atomic_swap_64(ptep, pte);
                                AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true);
                        }
                }