[src/trunk]: src/sys/arch Add DISABLE_INTERRUPT_SAVE(), like DISABLE_INTERRUP...

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/79b5fe3f75a7
branches:  trunk
changeset: 981154:79b5fe3f75a7
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Mon Mar 01 11:29:14 2021 +0000

description:
Add DISABLE_INTERRUPT_SAVE(), like DISABLE_INTERRUPT() but also returns
the previous state.

Use DISABLE_INTERRUPT_SAVE()/ENABLE_INTERRUPT() in pic_splfuncs instead
of cpsid()/cpsie(). The difference here is the caller no longer specifies
which bits to disable and enable; on arm32 we continue to use I32_bit and
on aarch64 we now consistently toggle both IRQ and FIQ state.

diffstat:

 sys/arch/aarch64/include/locore.h |   9 +++++----
 sys/arch/arm/include/cpufunc.h    |   5 +++--
 sys/arch/arm/pic/pic_splfuncs.c   |  15 ++++++++-------
 3 files changed, 16 insertions(+), 13 deletions(-)

diffs (93 lines):

diff -r f1fac4ba4a21 -r 79b5fe3f75a7 sys/arch/aarch64/include/locore.h
--- a/sys/arch/aarch64/include/locore.h Mon Mar 01 09:24:27 2021 +0000
+++ b/sys/arch/aarch64/include/locore.h Mon Mar 01 11:29:14 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.8 2021/02/20 19:27:35 jmcneill Exp $ */
+/* $NetBSD: locore.h,v 1.9 2021/03/01 11:29:14 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -58,11 +58,12 @@
 #define cpsie(psw)             daif_enable((psw))
 #define cpsid(psw)             daif_disable((psw))
 
-
-#define ENABLE_INTERRUPT()     \
+#define ENABLE_INTERRUPT()                                             \
        reg_daifclr_write((DAIF_I|DAIF_F) >> DAIF_SETCLR_SHIFT)
-#define DISABLE_INTERRUPT()    \
+#define DISABLE_INTERRUPT()                                            \
        reg_daifset_write((DAIF_I|DAIF_F) >> DAIF_SETCLR_SHIFT)
+#define DISABLE_INTERRUPT_SAVE()                                       \
+       daif_disable(DAIF_I|DAIF_F)
 
 #define DAIF_MASK              (DAIF_D|DAIF_A|DAIF_I|DAIF_F)
 
diff -r f1fac4ba4a21 -r 79b5fe3f75a7 sys/arch/arm/include/cpufunc.h
--- a/sys/arch/arm/include/cpufunc.h    Mon Mar 01 09:24:27 2021 +0000
+++ b/sys/arch/arm/include/cpufunc.h    Mon Mar 01 11:29:14 2021 +0000
@@ -353,8 +353,9 @@
 #define restore_interrupts(old_cpsr)                                   \
        (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
 
-#define        ENABLE_INTERRUPT()      cpsie(I32_bit)
-#define        DISABLE_INTERRUPT()     cpsid(I32_bit)
+#define        ENABLE_INTERRUPT()              cpsie(I32_bit)
+#define        DISABLE_INTERRUPT()             cpsid(I32_bit)
+#define        DISABLE_INTERRUPT_SAVE()        cpsid(I32_bit)
 
 static inline void cpsie(register_t psw) __attribute__((__unused__));
 static inline register_t cpsid(register_t psw) __attribute__((__unused__));
diff -r f1fac4ba4a21 -r 79b5fe3f75a7 sys/arch/arm/pic/pic_splfuncs.c
--- a/sys/arch/arm/pic/pic_splfuncs.c   Mon Mar 01 09:24:27 2021 +0000
+++ b/sys/arch/arm/pic/pic_splfuncs.c   Mon Mar 01 11:29:14 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pic_splfuncs.c,v 1.18 2021/02/22 21:16:25 jmcneill Exp $       */
+/*     $NetBSD: pic_splfuncs.c,v 1.19 2021/03/01 11:29:14 jmcneill Exp $       */
 /*-
  * Copyright (c) 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -28,7 +28,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pic_splfuncs.c,v 1.18 2021/02/22 21:16:25 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pic_splfuncs.c,v 1.19 2021/03/01 11:29:14 jmcneill Exp $");
 
 #define _INTR_PRIVATE
 #include <sys/param.h>
@@ -75,12 +75,13 @@
        const int oldipl = ci->ci_cpl;
        KDASSERT(panicstr || newipl <= ci->ci_cpl);
        if (newipl < ci->ci_cpl) {
-               register_t psw = cpsid(I32_bit);
+               register_t psw = DISABLE_INTERRUPT_SAVE();
                ci->ci_intr_depth++;
                pic_do_pending_ints(psw, newipl, NULL);
                ci->ci_intr_depth--;
-               if ((psw & I32_bit) == 0 || newipl == IPL_NONE)
-                       cpsie(I32_bit);
+               if ((psw & I32_bit) == 0 || newipl == IPL_NONE) {
+                       ENABLE_INTERRUPT();
+               }
                cpu_dosoftints();
        }
        return oldipl;
@@ -113,7 +114,7 @@
 static void __noinline
 splx_dopendingints(struct cpu_info *ci, const int savedipl)
 {
-       const register_t psw = cpsid(I32_bit);
+       const register_t psw = DISABLE_INTERRUPT_SAVE();
        ci->ci_intr_depth++;
        while ((ci->ci_pending_ipls & ~__BIT(savedipl)) > __BIT(savedipl)) {
                KASSERT(ci->ci_pending_ipls < __BIT(NIPL));
@@ -131,7 +132,7 @@
        }
        ci->ci_intr_depth--;
        if ((psw & I32_bit) == 0) {
-               cpsie(I32_bit);
+               ENABLE_INTERRUPT();
        }
 }
 #endif