[src/trunk]: src/sys/arch/mips/include Add PRID definition for newer SiByte S...

[simonb <simonb%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/87d633a8502d
branches:  trunk
changeset: 971871:87d633a8502d
user:      simonb <simonb%NetBSD.org@localhost>
date:      Thu May 07 11:43:28 2020 +0000

description:
Add PRID definition for newer SiByte SB1 cores (rev 0x11).
Add a constant for SiByte/BCRM cacheable coherent TLB cache attribute.

diffstat:

 sys/arch/mips/include/cpuregs.h |  6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diffs (27 lines):

diff -r 68ff75f9a2ee -r 87d633a8502d sys/arch/mips/include/cpuregs.h
--- a/sys/arch/mips/include/cpuregs.h   Thu May 07 11:24:47 2020 +0000
+++ b/sys/arch/mips/include/cpuregs.h   Thu May 07 11:43:28 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpuregs.h,v 1.96 2017/05/07 04:12:35 skrll Exp $       */
+/*     $NetBSD: cpuregs.h,v 1.97 2020/05/07 11:43:28 simonb Exp $      */
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -148,6 +148,7 @@
 
 #define        CCA_UNCACHED            2
 #define        CCA_CACHEABLE           3       /* cacheable non-coherent */
+#define        CCA_SB_CACHEABLE_COHERENT 5     /* cacheable coherent (SiByte ext) */
 #define        CCA_ACCEL               7       /* non-cached, write combining */
 
 /* CPU dependent mtc0 hazard hook */
@@ -964,7 +965,8 @@
 /*
  * CPU processor revision IDs for company ID == 4 (SiByte)
  */
-#define        MIPS_SB1        0x01    /* SiByte SB1                   ISA 64  */
+#define        MIPS_SB1        0x01    /* SiByte SB1                   ISA 64  */
+#define        MIPS_SB1_11     0x11    /* SiByte SB1 (rev 0x11)        ISA 64  */
 
 /*
  * CPU processor revision IDs for company ID == 5 (SandCraft)