[src/trunk]: src/sys/arch/x86/x86 Back out HPET delay & TSC changes to rule t...

[ad <ad%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/6f07bfce30e1
branches:  trunk
changeset: 971610:6f07bfce30e1
user:      ad <ad%NetBSD.org@localhost>
date:      Wed Apr 29 22:03:09 2020 +0000

description:
Back out HPET delay & TSC changes to rule them out as the cause for recent
hangs during boot etc.

diffstat:

 sys/arch/x86/x86/cpu.c |  60 ++++++++++++-------------------------------------
 1 files changed, 15 insertions(+), 45 deletions(-)

diffs (162 lines):

diff -r daf3cc4d406b -r 6f07bfce30e1 sys/arch/x86/x86/cpu.c
--- a/sys/arch/x86/x86/cpu.c    Wed Apr 29 21:00:42 2020 +0000
+++ b/sys/arch/x86/x86/cpu.c    Wed Apr 29 22:03:09 2020 +0000
@@ -1,7 +1,7 @@
-/*     $NetBSD: cpu.c,v 1.187 2020/04/25 15:26:18 bouyer Exp $ */
+/*     $NetBSD: cpu.c,v 1.188 2020/04/29 22:03:09 ad Exp $     */
 
 /*
- * Copyright (c) 2000-2020 NetBSD Foundation, Inc.
+ * Copyright (c) 2000-2012 NetBSD Foundation, Inc.
  * All rights reserved.
  *
  * This code is derived from software contributed to The NetBSD Foundation
@@ -62,7 +62,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.187 2020/04/25 15:26:18 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.188 2020/04/29 22:03:09 ad Exp $");
 
 #include "opt_ddb.h"
 #include "opt_mpbios.h"                /* for MPDEBUG */
@@ -73,7 +73,6 @@
 #include "lapic.h"
 #include "ioapic.h"
 #include "acpica.h"
-#include "hpet.h"
 
 #include <sys/param.h>
 #include <sys/proc.h>
@@ -120,7 +119,6 @@
 #endif
 
 #include <dev/ic/mc146818reg.h>
-#include <dev/ic/hpetvar.h>
 #include <i386/isa/nvram.h>
 #include <dev/isa/isareg.h>
 
@@ -204,8 +202,6 @@
 #endif
 struct cpu_info *cpu_starting;
 
-int (*cpu_nullop_ptr)(void *) = nullop;
-
 #ifdef MULTIPROCESSOR
 void           cpu_hatch(void *);
 static void    cpu_boot_secondary(struct cpu_info *ci);
@@ -437,11 +433,8 @@
         * must be done to allow booting other processors.
         */
        if (!again) {
-               /* Make sure DELAY() (likely i8254_delay()) is initialized. */
-               DELAY(1);
-
+               atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY);
                /* Basic init. */
-               atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY);
                cpu_intr_init(ci);
                cpu_get_tsc_freq(ci);
                cpu_init(ci);
@@ -458,6 +451,8 @@
                                lapic_calibrate_timer(ci);
                }
 #endif
+               /* Make sure DELAY() is initialized. */
+               DELAY(1);
                kcsan_cpu_init(ci);
                again = true;
        }
@@ -723,6 +718,7 @@
 
        if (ci != &cpu_info_primary) {
                /* Synchronize TSC */
+               wbinvd();
                atomic_or_32(&ci->ci_flags, CPUF_RUNNING);
                tsc_sync_ap(ci);
        } else {
@@ -738,14 +734,6 @@
        kcpuset_t *cpus;
        u_long i;
 
-#if NHPET > 0
-       /* Use HPET delay, and re-calibrate TSC on boot CPU using HPET. */
-       if (hpet_delay_p() && x86_delay == i8254_delay) {
-               delay_func = x86_delay = hpet_delay;
-               cpu_get_tsc_freq(curcpu());
-       }
-#endif
-
        /* Now that we know the number of CPUs, patch the text segment. */
        x86_patch(false);
 
@@ -854,6 +842,7 @@
                 */
                psl = x86_read_psl();
                x86_disable_intr();
+               wbinvd();
                tsc_sync_bp(ci);
                x86_write_psl(psl);
        }
@@ -884,6 +873,7 @@
                drift = ci->ci_data.cpu_cc_skew;
                psl = x86_read_psl();
                x86_disable_intr();
+               wbinvd();
                tsc_sync_bp(ci);
                x86_write_psl(psl);
                drift -= ci->ci_data.cpu_cc_skew;
@@ -929,6 +919,7 @@
         * Synchronize the TSC for the first time. Note that interrupts are
         * off at this point.
         */
+       wbinvd();
        atomic_or_32(&ci->ci_flags, CPUF_PRESENT);
        tsc_sync_ap(ci);
 
@@ -1319,8 +1310,7 @@
 void
 cpu_get_tsc_freq(struct cpu_info *ci)
 {
-       uint64_t freq = 0, t0, t1;
-       int64_t overhead;
+       uint64_t freq = 0, last_tsc;
 
        if (cpu_hascounter())
                freq = cpu_tsc_freq_cpuid(ci);
@@ -1329,31 +1319,11 @@
                /* Use TSC frequency taken from CPUID. */
                ci->ci_data.cpu_cc_freq = freq;
        } else {
-               /*
-                * Work out the approximate overhead involved below.
-                * Discard the result of the first go around the loop.
-                */
-               overhead = 0;           
-               for (int i = 0; i <= 8; i++) {
-                       __insn_barrier();
-                       t0 = cpu_counter_serializing();
-                       (*cpu_nullop_ptr)(NULL);
-                       t1 = cpu_counter_serializing();
-                       __insn_barrier();
-                       if (i > 0) {
-                               overhead += (t1 - t0);
-                       }
-               }
-               overhead >>= 3;
-
-               /* Now warm up x86_delay() and do the calibration. */
-               x86_delay(1);
-               __insn_barrier();
-               t0 = cpu_counter_serializing();
+               /* Calibrate TSC frequency. */
+               last_tsc = cpu_counter_serializing();
                x86_delay(100000);
-               t1 = cpu_counter_serializing();
-               __insn_barrier();
-               ci->ci_data.cpu_cc_freq = (t1 - t0 - overhead) * 10;
+               ci->ci_data.cpu_cc_freq =
+                   (cpu_counter_serializing() - last_tsc) * 10;
        }
 }