[src/trunk]: src/sys/arch/mips/include Use compiler defines to determine whic...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/1333bdaaacc4
branches:  trunk
changeset: 974714:1333bdaaacc4
user:      skrll <skrll%NetBSD.org@localhost>
date:      Sun Aug 09 08:13:09 2020 +0000

description:
Use compiler defines to determine which LLSCSYNC, et al
to provide.

This should fix mips builds.

diffstat:

 sys/arch/mips/include/asm.h |  18 ++++--------------
 1 files changed, 4 insertions(+), 14 deletions(-)

diffs (47 lines):

diff -r f133443a10e6 -r 1333bdaaacc4 sys/arch/mips/include/asm.h
--- a/sys/arch/mips/include/asm.h       Sun Aug 09 08:03:31 2020 +0000
+++ b/sys/arch/mips/include/asm.h       Sun Aug 09 08:13:09 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: asm.h,v 1.58 2020/08/06 10:00:20 skrll Exp $   */
+/*     $NetBSD: asm.h,v 1.59 2020/08/09 08:13:09 skrll Exp $   */
 
 /*
  * Copyright (c) 1992, 1993
@@ -54,10 +54,6 @@
 #ifndef _MIPS_ASM_H
 #define        _MIPS_ASM_H
 
-#include "opt_cputype.h"
-#include "opt_lockdebug.h"
-#include "opt_multiprocessor.h"
-
 #include <sys/cdefs.h>         /* for API selection */
 #include <mips/regdef.h>
 
@@ -517,23 +513,17 @@
 #define        NOP_L           /* nothing */
 #endif
 
-#if defined(MULTIPROCESSOR)
-#if defined(MIPS64_OCTEON)
+/* compiler define */
+#if defined(__OCTEON__)
                                /* early cnMIPS have erratum which means 2 */
 #define        LLSCSYNC        sync 4; sync 4
 #define        SYNC            sync 4          /* sync 4 == syncw - sync all writes */
 #define        BDSYNC          sync 4          /* sync 4 == syncw - sync all writes */
 #else
-#define        LLSCSYNC        /* nothing (something?) */
+#define        LLSCSYNC        sync
 #define        SYNC            sync
 #define        BDSYNC          sync
 #endif
-#else
-#define        LLSCSYNC        /* nothing */
-#define        SYNC            /* nothing */
-#define        BDSYNC          nop
-#endif /* defined(MULTIPROCESSOR) */
-
 
 /* CPU dependent hook for cp0 load delays */
 #if defined(MIPS1) || defined(MIPS2) || defined(MIPS3)