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[src/trunk]: src/sys/arch Finish CPU core support for Octeon Cavium CN70XX:
details: https://anonhg.NetBSD.org/src/rev/c94fbeba98fd
branches: trunk
changeset: 972995:c94fbeba98fd
user: simonb <simonb%NetBSD.org@localhost>
date: Mon Jun 15 07:48:12 2020 +0000
description:
Finish CPU core support for Octeon Cavium CN70XX:
- decode actual CPU name
- per CPU core reset logic (partially adapted from OpenBSD)
- handle Octeon 3 ioclock rate differences to other cores (from OpenBSD)
diffstat:
sys/arch/evbmips/cavium/machdep.c | 27 +--
sys/arch/mips/cavium/dev/octeon_uart.c | 8 +-
sys/arch/mips/cavium/octeon_misc.c | 273 +++++++++++++++++++++++++++++++++
sys/arch/mips/cavium/octeonreg.h | 66 +++++++
sys/arch/mips/cavium/octeonvar.h | 40 +++-
sys/arch/mips/conf/files.octeon | 3 +-
sys/arch/mips/mips/mips_machdep.c | 13 +-
7 files changed, 388 insertions(+), 42 deletions(-)
diffs (truncated from 570 to 300 lines):
diff -r 710237483fb9 -r c94fbeba98fd sys/arch/evbmips/cavium/machdep.c
--- a/sys/arch/evbmips/cavium/machdep.c Mon Jun 15 03:39:00 2020 +0000
+++ b/sys/arch/evbmips/cavium/machdep.c Mon Jun 15 07:48:12 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.13 2020/06/05 07:17:38 simonb Exp $ */
+/* $NetBSD: machdep.c,v 1.14 2020/06/15 07:48:12 simonb Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -115,7 +115,7 @@
#include "opt_cavium.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.13 2020/06/05 07:17:38 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.14 2020/06/15 07:48:12 simonb Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -191,7 +191,6 @@
mach_init(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3)
{
uint64_t btinfo_paddr;
- int corefreq;
/* clear the BSS segment */
memset(edata, 0, end - edata);
@@ -205,20 +204,10 @@
(struct octeon_btinfo *)MIPS_PHYS_TO_KSEG0(btinfo_paddr),
sizeof(octeon_btinfo));
- corefreq = octeon_btinfo.obt_eclock_hz;
-
- octeon_cal_timer(corefreq);
+ octeon_cal_timer(octeon_btinfo.obt_eclock_hz);
- switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) {
- case 0: cpu_setmodel("Cavium Octeon CN38XX/CN36XX"); break;
- case 1: cpu_setmodel("Cavium Octeon CN31XX/CN3020"); break;
- case 2: cpu_setmodel("Cavium Octeon CN3005/CN3010"); break;
- case 3: cpu_setmodel("Cavium Octeon CN58XX"); break;
- case 4: cpu_setmodel("Cavium Octeon CN5[4-7]XX"); break;
- case 6: cpu_setmodel("Cavium Octeon CN50XX"); break;
- case 7: cpu_setmodel("Cavium Octeon CN52XX"); break;
- default: cpu_setmodel("Cavium Octeon"); break;
- }
+ cpu_setmodel("Cavium Octeon %s",
+ octeon_cpu_model(mips_options.mips_cpu_id));
mach_init_vector();
@@ -459,11 +448,7 @@
*/
delay(80000);
- /* initiate chip soft-reset */
- uint64_t fuse = octeon_read_csr(CIU_FUSE);
- octeon_write_csr(CIU_SOFT_BIST, fuse);
- octeon_read_csr(CIU_SOFT_RST);
- octeon_write_csr(CIU_SOFT_RST, fuse);
+ octeon_soft_reset();
delay(1000000);
diff -r 710237483fb9 -r c94fbeba98fd sys/arch/mips/cavium/dev/octeon_uart.c
--- a/sys/arch/mips/cavium/dev/octeon_uart.c Mon Jun 15 03:39:00 2020 +0000
+++ b/sys/arch/mips/cavium/dev/octeon_uart.c Mon Jun 15 07:48:12 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_uart.c,v 1.5 2020/05/31 14:05:21 simonb Exp $ */
+/* $NetBSD: octeon_uart.c,v 1.6 2020/06/15 07:48:12 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: octeon_uart.c,v 1.5 2020/05/31 14:05:21 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: octeon_uart.c,v 1.6 2020/06/15 07:48:12 simonb Exp $");
#include "opt_octeon.h"
@@ -139,7 +139,7 @@
}
sc_com->sc_type = COM_TYPE_16550_NOERS;
- sc_com->sc_frequency = curcpu()->ci_cpu_freq;
+ sc_com->sc_frequency = octeon_ioclock_speed();
sc_com->enable = octuart_com_enable;
sc_com->disable = octuart_com_disable;
@@ -205,7 +205,7 @@
return comcnattach1(
®s,
speed,
- curcpu()->ci_cpu_freq,
+ octeon_ioclock_speed(),
COM_TYPE_16550_NOERS,
CONMODE);
}
diff -r 710237483fb9 -r c94fbeba98fd sys/arch/mips/cavium/octeon_misc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/cavium/octeon_misc.c Mon Jun 15 07:48:12 2020 +0000
@@ -0,0 +1,273 @@
+/* $NetBSD: octeon_misc.c,v 1.1 2020/06/15 07:48:12 simonb Exp $ */
+
+/*-
+ * Copyright (c) 2020 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Simon Burge.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 2009, 2010 Miodrag Vallat.
+ * Copyright (c) 2019 Visa Hankala.
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+/*
+ * Copyright (c) 2003-2004 Opsycon AB (www.opsycon.se / www.opsycon.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: octeon_misc.c,v 1.1 2020/06/15 07:48:12 simonb Exp $");
+
+#include <sys/param.h>
+
+#include <mips/cavium/octeonreg.h>
+#include <mips/cavium/octeonvar.h>
+#include <mips/cavium/dev/octeon_ciureg.h>
+
+int octeon_core_ver;
+
+/*
+ * Return the name of the CPU model we are running on.
+ * Side effect: sets the octeon_core_ver variable.
+ */
+const char *
+octeon_cpu_model(mips_prid_t cpu_id)
+{
+ const uint64_t fuse = octeon_xkphys_read_8(CIU_FUSE);
+ const int numcores = popcount64(fuse);
+ const int clock_mhz = curcpu()->ci_cpu_freq / 1000000;
+ const char *family;
+ const char *coremodel;
+ bool tested;
+ static char buf[sizeof("CNnnXX-NNNN (unverified)")] = {};
+
+ if (buf[0] != 0)
+ return buf; /* we've been here before */
+
+ /*
+ * Don't print "pass X.Y", but if needed:
+ * passhi = ((cpu_id >> 3) & 7) + '0';
+ * passlo = (cpu_id & 7) + '0';
+ * Note some chips use different representation for the pass number.
+ */
+
+#ifdef OCTEON_DEBUG
+ printf("cpuid = 0x%x\n", cpu_id);
+#endif
+
+ switch (numcores) {
+ case 1: coremodel = "10"; break;
+ case 2: coremodel = "20"; break;
+ case 3: coremodel = "25"; break;
+ case 4: coremodel = "30"; break;
+ case 5: coremodel = "32"; break;
+ case 6: coremodel = "34"; break;
+ case 7: coremodel = "38"; break;
+ case 8: coremodel = "40"; break;
+ case 9: coremodel = "42"; break;
+ case 10: coremodel = "45"; break;
+ case 11: coremodel = "48"; break;
+ case 12: coremodel = "50"; break;
+ case 13: coremodel = "52"; break;
+ case 14: coremodel = "55"; break;
+ case 15: coremodel = "58"; break;
+ case 16: coremodel = "60"; break;
+ case 24: coremodel = "70"; break;
+ case 32: coremodel = "80"; break;
+ case 40: coremodel = "85"; break;
+ case 44: coremodel = "88"; break;
+ case 48: coremodel = "90"; break;
+ default:
+ coremodel = "XX"; break;
+ }
+
+ /*
+ * Assume all CPU families haven't been tested unless explicitly
+ * noted. Sources of extra information for determining actual
+ * CPU models include chip documentation and U-Boot source code.
+ */
+ tested = false;
+
+ switch (MIPS_PRID_IMPL(cpu_id)) {
+ /* the order of these cases is the numeric value of MIPS_CNnnXX */
+ case MIPS_CN38XX:
+ family = "38"; /* XXX may also be family "36" or "37" */
+ octeon_core_ver = OCTEON_1;
+ break;
+ case MIPS_CN31XX:
+ family = "31"; /* XXX may also be model "3020" */
+ octeon_core_ver = OCTEON_1;
+ break;
+ case MIPS_CN30XX:
+ family = "30"; /* XXX half cache model is "3005" */
+ octeon_core_ver = OCTEON_1;
+ break;
+ case MIPS_CN58XX:
+ family = "58";
+ octeon_core_ver = OCTEON_PLUS;
+ break;
+ case MIPS_CN56XX:
+ family = "56"; /* XXX may also be family "54", "55" or "57" */
+ octeon_core_ver = OCTEON_PLUS;
+ break;
+ case MIPS_CN50XX:
+ family = "50";
+ octeon_core_ver = OCTEON_PLUS;
+ tested = true;
+ break;
+ case MIPS_CN52XX:
+ family = "52"; /* XXX may also be family "51" */
+ octeon_core_ver = OCTEON_PLUS;
+ break;
+ case MIPS_CN63XX:
+ family = "63"; /* XXX may also be family "62" */
+ octeon_core_ver = OCTEON_2;
+ break;
+ case MIPS_CN68XX:
+ family = "68";
+ octeon_core_ver = OCTEON_2;
+ break;
+ case MIPS_CN66XX:
+ family = "66";
+ octeon_core_ver = OCTEON_2;
+ break;
+ case MIPS_CN61XX:
+ family = "61"; /* XXX may also be family "60" */
+ octeon_core_ver = OCTEON_2;
+ break;
+ case MIPS_CN78XX:
+ family = "78"; /* XXX may also be family "76" or "77" */
+ octeon_core_ver = OCTEON_3;
+ break;
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