[src/trunk]: src/sys/arch/mips/include Define Octeon Cavium cache layouts for...

[simonb <simonb%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/87064026a97d
branches:  trunk
changeset: 972947:87064026a97d
user:      simonb <simonb%NetBSD.org@localhost>
date:      Sun Jun 14 08:43:07 2020 +0000

description:
Define Octeon Cavium cache layouts for various cnMIPS cores.

diffstat:

 sys/arch/mips/include/cache_octeon.h |  31 ++++++++++++++++++++++++++++++-
 1 files changed, 30 insertions(+), 1 deletions(-)

diffs (49 lines):

diff -r 7e93b616bdbd -r 87064026a97d sys/arch/mips/include/cache_octeon.h
--- a/sys/arch/mips/include/cache_octeon.h      Sun Jun 14 06:50:31 2020 +0000
+++ b/sys/arch/mips/include/cache_octeon.h      Sun Jun 14 08:43:07 2020 +0000
@@ -1,4 +1,7 @@
-/*     $NetBSD: cache_octeon.h,v 1.3 2019/04/11 09:18:55 simonb Exp $  */
+/*     $NetBSD: cache_octeon.h,v 1.4 2020/06/14 08:43:07 simonb Exp $  */
+
+#ifndef _MIPS_CACHE_OCTEON_H_
+#define _MIPS_CACHE_OCTEON_H_
 
 #define        CACHE_OCTEON_I                  0
 #define        CACHE_OCTEON_D                  1
@@ -8,6 +11,31 @@
 #define        CACHEOP_OCTEON_BITMAP_STORE             (3 << 2)        /* I */
 #define        CACHEOP_OCTEON_VIRTUAL_TAG_INV          (4 << 2)        /* D */
 
+#define        OCTEON_CACHELINE_SIZE                   128
+
+/*
+ * Note that for the Dcache the 50XX manual says 1 set per way (Config1
+ * register - DS=0 ("... actual is 1"), p173) as does U-boot sources,
+ * however this only adds up to an 8kB Dcache.  The 50XX manual
+ * elsewhere references a 16kB Dcache as does the CN50XX product brief.
+ * The original NetBSD code, current OpenBSD and Linux code all use 2
+ * sets per way. lmbench's "cache" program also detects a 16kB Dcache.
+ * So we assume that all Octeon 1 and Octeon Plus cores have a 16kB
+ * Dcache.
+ */
+#define        OCTEON_I_DCACHE_WAYS                    64
+#define        OCTEON_I_DCACHE_SETS                    2
+
+#define        OCTEON_II_DCACHE_SETS                   8
+#define        OCTEON_II_DCACHE_WAYS                   32
+#define        OCTEON_II_ICACHE_SETS                   8
+#define        OCTEON_II_ICACHE_WAYS                   37
+
+#define        OCTEON_III_DCACHE_SETS                  8
+#define        OCTEON_III_DCACHE_WAYS                  32
+#define        OCTEON_III_ICACHE_SETS                  16
+#define        OCTEON_III_ICACHE_WAYS                  39
+
 #if !defined(_LOCORE)
 
 /*
@@ -54,3 +82,4 @@
 void octeon_pdcache_wb_range(register_t va, vsize_t size);
 
 #endif /* !_LOCORE */
+#endif /* _MIPS_CACHE_OCTEON_H_ */