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[src/trunk]: src/sys/arch/mips/include Move MIPSNN_CFG3_ULRI so that it doesn...
details: https://anonhg.NetBSD.org/src/rev/9adb59f1bb2f
branches: trunk
changeset: 972901:9adb59f1bb2f
user: simonb <simonb%NetBSD.org@localhost>
date: Sat Jun 13 14:41:24 2020 +0000
description:
Move MIPSNN_CFG3_ULRI so that it doesn't appear in some random position
among the other config3 register definitions.
diffstat:
sys/arch/mips/include/mipsNN.h | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diffs (29 lines):
diff -r e898fe23c05a -r 9adb59f1bb2f sys/arch/mips/include/mipsNN.h
--- a/sys/arch/mips/include/mipsNN.h Sat Jun 13 14:39:07 2020 +0000
+++ b/sys/arch/mips/include/mipsNN.h Sat Jun 13 14:41:24 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mipsNN.h,v 1.7 2020/06/13 14:39:07 simonb Exp $ */
+/* $NetBSD: mipsNN.h,v 1.8 2020/06/13 14:41:24 simonb Exp $ */
/*
* Copyright 2000, 2001
@@ -239,9 +239,6 @@
/* "CMGCR" (R): Coherency Manager memory-mapped Global Configuration Register Space is implemented. */
#define MIPSNN_CFG3_CMGCR 0x20000000
-/* "ULRI" (R): UserLocal register is implemented. */
-#define MIPSNN_CFG3_ULRI 0x00002000
-
/* "IPLW" (R): Width of Status[IPL] and Cause[RIPL] fields. */
#define MIPSNN_CFG3_IPLW_MASK 0x00600000
#define MIPSNN_CFG3_IPLW_SHIFT 21
@@ -271,6 +268,9 @@
#define MIPSNN_CFG3_ISA_MIPS64_OOR 2 /* both, MIPS64 out of reset */
#define MIPSNN_CFG3_ISA_microMIPS64_OOR 3 /* both, microMIPS64 OOR */
+/* "ULRI" (R): UserLocal register is implemented. */
+#define MIPSNN_CFG3_ULRI 0x00002000
+
/* "DSP2P" (R): DSP v2 ASE extension present. */
#define MIPSNN_CFG3_DSP2P 0x00000800
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