[src/trunk]: src/sys/arch/aarch64 Add some more id_aa64pfr0_el1 bits.

[riastradh <riastradh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/54f5a0b002e3
branches:  trunk
changeset: 972959:54f5a0b002e3
user:      riastradh <riastradh%NetBSD.org@localhost>
date:      Sun Jun 14 16:10:18 2020 +0000

description:
Add some more id_aa64pfr0_el1 bits.

diffstat:

 sys/arch/aarch64/aarch64/cpu.c    |  20 ++++++++++++++++++--
 sys/arch/aarch64/include/armreg.h |  22 +++++++++++++++++++++-
 2 files changed, 39 insertions(+), 3 deletions(-)

diffs (84 lines):

diff -r 18034704028d -r 54f5a0b002e3 sys/arch/aarch64/aarch64/cpu.c
--- a/sys/arch/aarch64/aarch64/cpu.c    Sun Jun 14 15:12:56 2020 +0000
+++ b/sys/arch/aarch64/aarch64/cpu.c    Sun Jun 14 16:10:18 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.46 2020/05/30 17:50:39 jmcneill Exp $ */
+/* $NetBSD: cpu.c,v 1.47 2020/06/14 16:10:18 riastradh Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.46 2020/05/30 17:50:39 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.47 2020/06/14 16:10:18 riastradh Exp $");
 
 #include "locators.h"
 #include "opt_arm_debug.h"
@@ -343,6 +343,16 @@
        aprint_verbose_dev(self, "auxID=0x%" PRIx64, ci->ci_id.ac_aa64isar0);
 
        /* PFR0 */
+       switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_CSV3)) {
+       case ID_AA64PFR0_EL1_CSV3_IMPL:
+               aprint_verbose(", CSV3");
+               break;
+       }
+       switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_CSV2)) {
+       case ID_AA64PFR0_EL1_CSV2_IMPL:
+               aprint_verbose(", CSV2");
+               break;
+       }
        switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_GIC)) {
        case ID_AA64PFR0_EL1_GIC_CPUIF_EN:
                aprint_verbose(", GICv3");
@@ -384,6 +394,12 @@
                break;
        }
 
+       /* PFR0:DIT -- data-independent timing support */
+       switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_DIT)) {
+       case ID_AA64PFR0_EL1_DIT_IMPL:
+               aprint_verbose(", DIT");
+               break;
+       }
 
        /* PFR0:AdvSIMD */
        switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_ADVSIMD)) {
diff -r 18034704028d -r 54f5a0b002e3 sys/arch/aarch64/include/armreg.h
--- a/sys/arch/aarch64/include/armreg.h Sun Jun 14 15:12:56 2020 +0000
+++ b/sys/arch/aarch64/include/armreg.h Sun Jun 14 16:10:18 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.48 2020/05/28 12:41:15 skrll Exp $ */
+/* $NetBSD: armreg.h,v 1.49 2020/06/14 16:10:18 riastradh Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -1305,6 +1305,26 @@
 #define        CNTCTL_ENABLE           __BIT(0)        // Timer Enabled
 
 // ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0
+#define        ID_AA64PFR0_EL1_CSV3            __BITS(63,60) // Speculative fault data
+#define         ID_AA64PFR0_EL1_CSV3_NONE      0
+#define         ID_AA64PFR0_EL1_CSV3_IMPL      1
+#define        ID_AA64PFR0_EL1_CSV2            __BITS(59,56) // Speculative branches
+#define         ID_AA64PFR0_EL1_CSV2_NONE      0
+#define         ID_AA64PFR0_EL1_CSV2_IMPL      1
+// reserved [55:52]
+#define        ID_AA64PFR0_EL1_DIT             __BITS(51,48) // Data-indep. timing
+#define         ID_AA64PFR0_EL1_DIT_NONE       0
+#define         ID_AA64PFR0_EL1_DIT_IMPL       1
+#define        ID_AA64PFR0_EL1_AMU             __BITS(47,44) // Activity monitors ext.
+#define         ID_AA64PFR0_EL1_AMU_NONE       0
+#define         ID_AA64PFR0_EL1_AMU_IMPLv8_4   1
+#define         ID_AA64PFR0_EL1_AMU_IMPLv8_6   2
+#define        ID_AA64PFR0_EL1_MPAM            __BITS(43,40) // MPAM Extension
+#define         ID_AA64PFR0_EL1_MPAM_NONE      0
+#define         ID_AA64PFR0_EL1_MPAM_IMPL      1
+#define        ID_AA64PFR0_EL1_SEL2            __BITS(43,40) // Secure EL2
+#define         ID_AA64PFR0_EL1_SEL2_NONE      0
+#define         ID_AA64PFR0_EL1_SEL2_IMPL      1
 #define        ID_AA64PFR0_EL1_SVE             __BITS(35,32) // Scalable Vector
 #define         ID_AA64PFR0_EL1_SVE_NONE        0
 #define         ID_AA64PFR0_EL1_SVE_IMPL        1