[src/trunk]: src/sys/arch/mips/mips Use 32 byte cacheline ops (not 16 byte on...

[tsutsui <tsutsui%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/e5595aebaaf8
branches:  trunk
changeset: 972954:e5595aebaaf8
user:      tsutsui <tsutsui%NetBSD.org@localhost>
date:      Sun Jun 14 14:16:49 2020 +0000

description:
Use 32 byte cacheline ops (not 16 byte ones) for R5000 picache.  PR/55138

Commented "I think this is bad copy&paste" from skrll@.
No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.

diffstat:

 sys/arch/mips/mips/cache.c |  8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diffs (32 lines):

diff -r d0ef92f8d0e0 -r e5595aebaaf8 sys/arch/mips/mips/cache.c
--- a/sys/arch/mips/mips/cache.c        Sun Jun 14 14:02:39 2020 +0000
+++ b/sys/arch/mips/mips/cache.c        Sun Jun 14 14:16:49 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.c,v 1.66 2020/06/14 12:58:01 simonb Exp $        */
+/*     $NetBSD: cache.c,v 1.67 2020/06/14 14:16:49 tsutsui Exp $       */
 
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.66 2020/06/14 12:58:01 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.67 2020/06/14 14:16:49 tsutsui Exp $");
 
 #include "opt_cputype.h"
 #include "opt_mips_cache.h"
@@ -495,11 +495,11 @@
                case 32:
                        /* used internally by mipsNN_picache_sync_range */
                        mco->mco_intern_icache_sync_range =
-                           cache_r4k_icache_hit_inv_16;
+                           cache_r4k_icache_hit_inv_32;
 
                        /* used internally by mipsNN_picache_sync_range_index */
                        mco->mco_intern_icache_sync_range_index =
-                           cache_r4k_icache_index_inv_16;
+                           cache_r4k_icache_index_inv_32;
                        break;
 
                default: