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[src/trunk]: src/sys/arch/mips/cavium/dev Remove more snprintb _BITS bits.
details: https://anonhg.NetBSD.org/src/rev/3ad55d86e9be
branches: trunk
changeset: 973158:3ad55d86e9be
user: simonb <simonb%NetBSD.org@localhost>
date: Mon Jun 22 12:26:11 2020 +0000
description:
Remove more snprintb _BITS bits.
diffstat:
sys/arch/mips/cavium/dev/octeon_bootbusreg.h | 29 +--------
sys/arch/mips/cavium/dev/octeon_ciureg.h | 40 +-----------
sys/arch/mips/cavium/dev/octeon_fpareg.h | 20 +-----
sys/arch/mips/cavium/dev/octeon_gmxreg.h | 89 +-------------------------
sys/arch/mips/cavium/dev/octeon_pipreg.h | 98 +---------------------------
sys/arch/mips/cavium/dev/octeon_powreg.h | 92 +--------------------------
sys/arch/mips/cavium/dev/octeon_usbcreg.h | 38 +----------
7 files changed, 7 insertions(+), 399 deletions(-)
diffs (truncated from 496 to 300 lines):
diff -r 3a1cb28f029c -r 3ad55d86e9be sys/arch/mips/cavium/dev/octeon_bootbusreg.h
--- a/sys/arch/mips/cavium/dev/octeon_bootbusreg.h Mon Jun 22 12:21:02 2020 +0000
+++ b/sys/arch/mips/cavium/dev/octeon_bootbusreg.h Mon Jun 22 12:26:11 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_bootbusreg.h,v 1.2 2020/06/22 03:05:07 simonb Exp $ */
+/* $NetBSD: octeon_bootbusreg.h,v 1.3 2020/06/22 12:26:11 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -116,33 +116,6 @@
#define MIO_BOOT_BIST_STAT_LOC UINT64_C(0x0000000000000002)
#define MIO_BOOT_BIST_STAT_NCBI UINT64_C(0x0000000000000001)
-#define MIO_BOOT_REG_CFG0_BITS MIO_BOOT_REG_CFGN_BITS
-#define MIO_BOOT_REG_CFG1_BITS MIO_BOOT_REG_CFGN_BITS
-#define MIO_BOOT_REG_CFG2_BITS MIO_BOOT_REG_CFGN_BITS
-#define MIO_BOOT_REG_CFG3_BITS MIO_BOOT_REG_CFGN_BITS
-#define MIO_BOOT_REG_CFG4_BITS MIO_BOOT_REG_CFGN_BITS
-#define MIO_BOOT_REG_CFG5_BITS MIO_BOOT_REG_CFGN_BITS
-#define MIO_BOOT_REG_CFG6_BITS MIO_BOOT_REG_CFGN_BITS
-#define MIO_BOOT_REG_CFG7_BITS MIO_BOOT_REG_CFGN_BITS
-
-#define MIO_BOOT_REG_TIM0_BITS MIO_BOOT_REG_TIMN_BITS
-#define MIO_BOOT_REG_TIM1_BITS MIO_BOOT_REG_TIMN_BITS
-#define MIO_BOOT_REG_TIM2_BITS MIO_BOOT_REG_TIMN_BITS
-#define MIO_BOOT_REG_TIM3_BITS MIO_BOOT_REG_TIMN_BITS
-#define MIO_BOOT_REG_TIM4_BITS MIO_BOOT_REG_TIMN_BITS
-#define MIO_BOOT_REG_TIM5_BITS MIO_BOOT_REG_TIMN_BITS
-#define MIO_BOOT_REG_TIM6_BITS MIO_BOOT_REG_TIMN_BITS
-#define MIO_BOOT_REG_TIM7_BITS MIO_BOOT_REG_TIMN_BITS
-
-#define MIO_BOOT_LOC_CFG0_BITS MIO_BOOT_LOC_CFGN_BITS
-#define MIO_BOOT_LOC_CFG1_BITS MIO_BOOT_LOC_CFGN_BITS
-#define MIO_BOOT_LOC_CFG2_BITS MIO_BOOT_LOC_CFGN_BITS
-#define MIO_BOOT_LOC_CFG3_BITS MIO_BOOT_LOC_CFGN_BITS
-#define MIO_BOOT_LOC_CFG4_BITS MIO_BOOT_LOC_CFGN_BITS
-#define MIO_BOOT_LOC_CFG5_BITS MIO_BOOT_LOC_CFGN_BITS
-#define MIO_BOOT_LOC_CFG6_BITS MIO_BOOT_LOC_CFGN_BITS
-#define MIO_BOOT_LOC_CFG7_BITS MIO_BOOT_LOC_CFGN_BITS
-
/* ---- bus_space */
#define MIO_BOOT_REG_CFG0_OFFSET 0x0000
diff -r 3a1cb28f029c -r 3ad55d86e9be sys/arch/mips/cavium/dev/octeon_ciureg.h
--- a/sys/arch/mips/cavium/dev/octeon_ciureg.h Mon Jun 22 12:21:02 2020 +0000
+++ b/sys/arch/mips/cavium/dev/octeon_ciureg.h Mon Jun 22 12:26:11 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_ciureg.h,v 1.8 2020/06/22 03:05:07 simonb Exp $ */
+/* $NetBSD: octeon_ciureg.h,v 1.9 2020/06/22 12:26:11 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -263,42 +263,4 @@
#define CIU_PCI_INTA_XXX_63_2 UINT64_C(0xfffffffffffffffc)
#define CIU_PCI_INTA_INT UINT64_C(0x0000000000000003)
-#define CIU_INT0_SUM0_BITS CIU_INTX_SUM0_BITS
-#define CIU_INT1_SUM0_BITS CIU_INTX_SUM0_BITS
-#define CIU_INT2_SUM0_BITS CIU_INTX_SUM0_BITS
-#define CIU_INT3_SUM0_BITS CIU_INTX_SUM0_BITS
-#define CIU_INT32_SUM0_BITS CIU_INTX_SUM0_BITS
-
-#define CIU_INT0_EN0_BITS CIU_INTX_EN0_BITS
-#define CIU_INT1_EN0_BITS CIU_INTX_EN0_BITS
-#define CIU_INT2_EN0_BITS CIU_INTX_EN0_BITS
-#define CIU_INT3_EN0_BITS CIU_INTX_EN0_BITS
-#define CIU_INT32_EN0_BITS CIU_INTX_EN0_BITS
-
-#define CIU_INT0_EN1_BITS CIU_INTX_EN1_BITS
-#define CIU_INT1_EN1_BITS CIU_INTX_EN1_BITS
-#define CIU_INT2_EN1_BITS CIU_INTX_EN1_BITS
-#define CIU_INT3_EN1_BITS CIU_INTX_EN1_BITS
-#define CIU_INT32_EN1_BITS CIU_INTX_EN1_BITS
-
-#define CIU_TIM0_BITS CIU_TIMX_BITS
-#define CIU_TIM1_BITS CIU_TIMX_BITS
-#define CIU_TIM2_BITS CIU_TIMX_BITS
-#define CIU_TIM3_BITS CIU_TIMX_BITS
-#define CIU_TIM32_BITS CIU_TIMX_BITS
-
-#define CIU_WDOG0_BITS CIU_WDOGX_BITS
-#define CIU_WDOG1_BITS CIU_WDOGX_BITS
-
-#if 0
-#define CIU_PP_POKE0_BITS CIU_PP_POKEX_BITS
-#define CIU_PP_POKE1_BITS CIU_PP_POKEX_BITS
-#endif
-
-#define CIU_MBOX_SET0_BITS CIU_MBOX_SETX_BITS
-#define CIU_MBOX_SET1_BITS CIU_MBOX_SETX_BITS
-
-#define CIU_MBOX_CLR0_BITS CIU_MBOX_CLRX_BITS
-#define CIU_MBOX_CLR1_BITS CIU_MBOX_CLRX_BITS
-
#endif /* _OCTEON_CIUREG_H_ */
diff -r 3a1cb28f029c -r 3ad55d86e9be sys/arch/mips/cavium/dev/octeon_fpareg.h
--- a/sys/arch/mips/cavium/dev/octeon_fpareg.h Mon Jun 22 12:21:02 2020 +0000
+++ b/sys/arch/mips/cavium/dev/octeon_fpareg.h Mon Jun 22 12:26:11 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_fpareg.h,v 1.3 2020/06/22 03:05:07 simonb Exp $ */
+/* $NetBSD: octeon_fpareg.h,v 1.4 2020/06/22 12:26:11 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -159,24 +159,6 @@
#define FPA_QUE_ACT_ACT_QUE UINT64_C(0x000000001c000000)
#define FPA_QUE_ACT_ACT_INDX UINT64_C(0x0000000003ffffff)
-#define FPA_QUE0_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
-#define FPA_QUE1_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
-#define FPA_QUE2_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
-#define FPA_QUE3_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
-#define FPA_QUE4_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
-#define FPA_QUE5_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
-#define FPA_QUE6_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
-#define FPA_QUE7_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
-
-#define FPA_QUE0_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
-#define FPA_QUE1_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
-#define FPA_QUE2_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
-#define FPA_QUE3_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
-#define FPA_QUE4_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
-#define FPA_QUE5_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
-#define FPA_QUE6_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
-#define FPA_QUE7_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
-
/* ---- operations */
/*
diff -r 3a1cb28f029c -r 3ad55d86e9be sys/arch/mips/cavium/dev/octeon_gmxreg.h
--- a/sys/arch/mips/cavium/dev/octeon_gmxreg.h Mon Jun 22 12:21:02 2020 +0000
+++ b/sys/arch/mips/cavium/dev/octeon_gmxreg.h Mon Jun 22 12:26:11 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_gmxreg.h,v 1.3 2020/06/22 03:05:07 simonb Exp $ */
+/* $NetBSD: octeon_gmxreg.h,v 1.4 2020/06/22 12:26:11 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -626,91 +626,4 @@
#define GMX0_BASE_IF0 0x0001180008000000ULL
#define GMX0_BASE_IF_SIZE (GMX0_BASE_PORT_SIZE * GMX_PORT_NUNITS)
-#define GMX0_RX0_INT_REG_BITS RXN_INT_REG_BITS
-#define GMX0_RX0_INT_EN_BITS RXN_INT_EN_BITS
-#define GMX0_PRT0_CFG_BITS PRTN_CFG_BITS
-#define GMX0_RX0_FRM_CTL_BITS RXN_FRM_CTL_BITS
-#define GMX0_RX0_FRM_CHK_BITS RXN_FRM_CHK_BITS
-#define GMX0_RX0_FRM_MIN_BITS NULL//RXN_FRM_MIN_BITS
-#define GMX0_RX0_FRM_MAX_BITS NULL//RXN_FRM_MAX_BITS
-#define GMX0_RX0_JABBER_BITS RXN_JABBER_BITS
-#define GMX0_RX0_DECISION_BITS RXN_DECISION_BITS
-#define GMX0_RX0_UDD_SKP_BITS RXN_UDD_SKP_BITS
-#define GMX0_RX0_STATS_CTL_BITS RXN_STATS_CTL_BITS
-#define GMX0_RX0_IFG_BITS RXN_IFG_BITS
-#define GMX0_RX0_RX_INBND_BITS RXN_RX_INBND_BITS
-#define GMX0_RX0_STATS_PKTS_BITS RXN_STATS_PKTS_BITS
-#define GMX0_RX0_STATS_OCTS_BITS RXN_STATS_OCTS_BITS
-#define GMX0_RX0_STATS_PKTS_CTL_BITS RXN_STATS_PKTS_CTL_BITS
-#define GMX0_RX0_STATS_OCTS_CTL_BITS RXN_STATS_OCTS_CTL_BITS
-#define GMX0_RX0_STATS_PKTS_DMAC_BITS RXN_STATS_PKTS_DMAC_BITS
-#define GMX0_RX0_STATS_OCTS_DMAC_BITS RXN_STATS_OCTS_DMAC_BITS
-#define GMX0_RX0_STATS_PKTS_DRP_BITS RXN_STATS_PKTS_DRP_BITS
-#define GMX0_RX0_STATS_OCTS_DRP_BITS RXN_STATS_OCTS_DRP_BITS
-#define GMX0_RX0_STATS_PKTS_BAD_BITS RXN_STATS_PKTS_BAD_BITS
-#define GMX0_RX0_ADR_CTL_BITS RXN_ADR_CTL_BITS
-#define GMX0_RX0_ADR_CAM_EN_BITS RXN_ADR_CAM_EN_BITS
-#define GMX0_RX0_ADR_CAM0_BITS NULL//RXN_ADR_CAM0_BITS
-#define GMX0_RX0_ADR_CAM1_BITS NULL//RXN_ADR_CAM1_BITS
-#define GMX0_RX0_ADR_CAM2_BITS NULL//RXN_ADR_CAM2_BITS
-#define GMX0_RX0_ADR_CAM3_BITS NULL//RXN_ADR_CAM3_BITS
-#define GMX0_RX0_ADR_CAM4_BITS NULL//RXN_ADR_CAM4_BITS
-#define GMX0_RX0_ADR_CAM5_BITS NULL//RXN_ADR_CAM5_BITS
-#define GMX0_TX0_CLK_BITS TXN_CLK_BITS
-#define GMX0_TX0_THRESH_BITS TXN_THRESH_BITS
-#define GMX0_TX0_APPEND_BITS TXN_APPEND_BITS
-#define GMX0_TX0_SLOT_BITS TXN_SLOT_BITS
-#define GMX0_TX0_BURST_BITS TXN_BURST_BITS
-#define GMX0_SMAC0_BITS NULL//SMAC0_BITS
-#define GMX0_TX0_PAUSE_PKT_TIME_BITS TXN_PAUSE_PKT_TIME_BITS
-#define GMX0_TX0_MIN_PKT_BITS TXN_MIN_PKT_BITS
-#define GMX0_TX0_PAUSE_PKT_INTERVAL_BITS TXN_PAUSE_PKT_INTERVAL_BITS
-#define GMX0_TX0_SOFT_PAUSE_BITS TXN_SOFT_PAUSE_BITS
-#define GMX0_TX0_PAUSE_TOGO_BITS TXN_PAUSE_TOGO_BITS
-#define GMX0_TX0_PAUSE_ZERO_BITS TXN_PAUSE_ZERO_BITS
-#define GMX0_TX0_STATS_CTL_BITS TXN_STATS_CTL_BITS
-#define GMX0_TX0_CTL_BITS TXN_CTL_BITS
-#define GMX0_TX0_STAT0_BITS TXN_STAT0_BITS
-#define GMX0_TX0_STAT1_BITS TXN_STAT1_BITS
-#define GMX0_TX0_STAT2_BITS TXN_STAT2_BITS
-#define GMX0_TX0_STAT3_BITS TXN_STAT3_BITS
-#define GMX0_TX0_STAT4_BITS TXN_STAT4_BITS
-#define GMX0_TX0_STAT5_BITS TXN_STAT5_BITS
-#define GMX0_TX0_STAT6_BITS TXN_STAT6_BITS
-#define GMX0_TX0_STAT7_BITS TXN_STAT7_BITS
-#define GMX0_TX0_STAT8_BITS TXN_STAT8_BITS
-#define GMX0_TX0_STAT9_BITS TXN_STAT9_BITS
-#define GMX0_BIST0_BITS NULL//BIST0_BITS
-#define GMX0_RX_PRTS_BITS RX_PRTS_BITS
-#define GMX0_RX_BP_DROP0_BITS RX_BP_DROPN_BITS
-#define GMX0_RX_BP_ON0_BITS RX_BP_ONN_BITS
-#define GMX0_RX_BP_OFF0_BITS RX_BP_OFFN_BITS
-#define GMX0_RX_BP_DROP1_BITS RX_BP_DROPN_BITS
-#define GMX0_RX_BP_ON1_BITS RX_BP_ONN_BITS
-#define GMX0_RX_BP_OFF1_BITS RX_BP_OFFN_BITS
-#define GMX0_RX_BP_DROP2_BITS RX_BP_DROPN_BITS
-#define GMX0_RX_BP_ON2_BITS RX_BP_ONN_BITS
-#define GMX0_RX_BP_OFF2_BITS RX_BP_OFFN_BITS
-#define GMX0_TX_PRTS_BITS TX_PRTS_BITS
-#define GMX0_TX_IFG_BITS TX_IFG_BITS
-#define GMX0_TX_JAM_BITS TX_JAM_BITS
-#define GMX0_TX_COL_ATTEMPT_BITS TX_COL_ATTEMPT_BITS
-#define GMX0_TX_PAUSE_PKT_DMAC_BITS TX_PAUSE_PKT_DMAC_BITS
-#define GMX0_TX_PAUSE_PKT_TYPE_BITS TX_PAUSE_PKT_TYPE_BITS
-#define GMX0_TX_OVR_BP_BITS TX_OVR_BP_BITS
-#define GMX0_TX_BP_BITS TX_BP_BITS
-#define GMX0_TX_CORRUPT_BITS TX_CORRUPT_BITS
-#define GMX0_RX_PRT_INFO_BITS RX_PRT_INFO_BITS
-#define GMX0_TX_LFSR_BITS TX_LFSR_BITS
-#define GMX0_TX_INT_REG_BITS TX_INT_REG_BITS
-#define GMX0_TX_INT_EN_BITS TX_INT_EN_BITS
-#define GMX0_NXA_ADR_BITS NXA_ADR_BITS
-#define GMX0_BAD_REG_BITS BAD_REG_BITS
-#define GMX0_STAT_BP_BITS STAT_BP_BITS
-#define GMX0_TX_CLK_MSK0_BITS TX_CLK_MSKN_BITS
-#define GMX0_TX_CLK_MSK1_BITS TX_CLK_MSKN_BITS
-#define GMX0_TX_CLK_MSK2_BITS TX_CLK_MSKN_BITS
-#define GMX0_RX_TX_STATUS_BITS RX_TX_STATUS_BITS
-#define GMX0_INF_MODE_BITS INF_MODE_BITS
-
#endif /* _OCTEON_GMXREG_H_ */
diff -r 3a1cb28f029c -r 3ad55d86e9be sys/arch/mips/cavium/dev/octeon_pipreg.h
--- a/sys/arch/mips/cavium/dev/octeon_pipreg.h Mon Jun 22 12:21:02 2020 +0000
+++ b/sys/arch/mips/cavium/dev/octeon_pipreg.h Mon Jun 22 12:26:11 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_pipreg.h,v 1.3 2020/06/22 03:05:07 simonb Exp $ */
+/* $NetBSD: octeon_pipreg.h,v 1.4 2020/06/22 12:26:11 simonb Exp $ */
/*
* Copyright (c) 2007 Internet Initiative Japan, Inc.
@@ -623,100 +623,4 @@
#define PIP_GMX_FCS_ERR PIP_WQE_WORD2_RE_OPCODE_GMXFCS
#define PIP_ALIGN_ERR PIP_WQE_WORD2_RE_OPCODE_ALIGN
-#define PIP_DEC_IPSEC0_BITS PIP_DEC_IPSECN_BITS
-#define PIP_DEC_IPSEC1_BITS PIP_DEC_IPSECN_BITS
-#define PIP_DEC_IPSEC2_BITS PIP_DEC_IPSECN_BITS
-#define PIP_DEC_IPSEC3_BITS PIP_DEC_IPSECN_BITS
-
-#define PIP_QOS_VLAN0_BITS PIP_QOS_VLANN_BITS
-#define PIP_QOS_VLAN1_BITS PIP_QOS_VLANN_BITS
-#define PIP_QOS_VLAN2_BITS PIP_QOS_VLANN_BITS
-#define PIP_QOS_VLAN3_BITS PIP_QOS_VLANN_BITS
-#define PIP_QOS_VLAN4_BITS PIP_QOS_VLANN_BITS
-#define PIP_QOS_VLAN5_BITS PIP_QOS_VLANN_BITS
-#define PIP_QOS_VLAN6_BITS PIP_QOS_VLANN_BITS
-#define PIP_QOS_VLAN7_BITS PIP_QOS_VLANN_BITS
-
-#define PIP_QOS_WATCH0_BITS PIP_QOS_WATCHN_BITS
-#define PIP_QOS_WATCH1_BITS PIP_QOS_WATCHN_BITS
-#define PIP_QOS_WATCH2_BITS PIP_QOS_WATCHN_BITS
-#define PIP_QOS_WATCH3_BITS PIP_QOS_WATCHN_BITS
-
-#define PIP_PRT_CFG0_BITS PIP_PRT_CFGN_BITS
-#define PIP_PRT_CFG1_BITS PIP_PRT_CFGN_BITS
-#define PIP_PRT_CFG2_BITS PIP_PRT_CFGN_BITS
-#define PIP_PRT_CFG32_BITS PIP_PRT_CFGN_BITS
-
-#define PIP_PRT_TAG0_BITS PIP_PRT_TAGN_BITS
-#define PIP_PRT_TAG1_BITS PIP_PRT_TAGN_BITS
-#define PIP_PRT_TAG2_BITS PIP_PRT_TAGN_BITS
-#define PIP_PRT_TAG32_BITS PIP_PRT_TAGN_BITS
-/* PIP_QOS_DIFF[0-63] */
-
-#define PIP_STAT0_PRT0_BITS PIP_STAT0_PRTN_BITS
-#define PIP_STAT0_PRT1_BITS PIP_STAT0_PRTN_BITS
-#define PIP_STAT0_PRT2_BITS PIP_STAT0_PRTN_BITS
-#define PIP_STAT0_PRT32_BITS PIP_STAT0_PRTN_BITS
-
-#define PIP_STAT1_PRT0_BITS PIP_STAT1_PRTN_BITS
-#define PIP_STAT1_PRT1_BITS PIP_STAT1_PRTN_BITS
-#define PIP_STAT1_PRT2_BITS PIP_STAT1_PRTN_BITS
-#define PIP_STAT1_PRT32_BITS PIP_STAT1_PRTN_BITS
-
-#define PIP_STAT2_PRT0_BITS PIP_STAT2_PRTN_BITS
-#define PIP_STAT2_PRT1_BITS PIP_STAT2_PRTN_BITS
-#define PIP_STAT2_PRT2_BITS PIP_STAT2_PRTN_BITS
-#define PIP_STAT2_PRT32_BITS PIP_STAT2_PRTN_BITS
-
-#define PIP_STAT3_PRT0_BITS PIP_STAT3_PRTN_BITS
-#define PIP_STAT3_PRT1_BITS PIP_STAT3_PRTN_BITS
-#define PIP_STAT3_PRT2_BITS PIP_STAT3_PRTN_BITS
-#define PIP_STAT3_PRT32_BITS PIP_STAT3_PRTN_BITS
-
-#define PIP_STAT4_PRT0_BITS PIP_STAT4_PRTN_BITS
-#define PIP_STAT4_PRT1_BITS PIP_STAT4_PRTN_BITS
-#define PIP_STAT4_PRT2_BITS PIP_STAT4_PRTN_BITS
-#define PIP_STAT4_PRT32_BITS PIP_STAT4_PRTN_BITS
-
-#define PIP_STAT5_PRT0_BITS PIP_STAT5_PRTN_BITS
-#define PIP_STAT5_PRT1_BITS PIP_STAT5_PRTN_BITS
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