[src/trunk]: src/sys/arch/mips/mips Increase readability by reducing #ifdef u...

[simonb <simonb%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/f395b2775b1c
branches:  trunk
changeset: 972746:f395b2775b1c
user:      simonb <simonb%NetBSD.org@localhost>
date:      Sat Jun 06 14:30:44 2020 +0000

description:
Increase readability by reducing #ifdef using a macro.

diffstat:

 sys/arch/mips/mips/cache_octeon.c |  62 +++++++++++++++++---------------------
 1 files changed, 28 insertions(+), 34 deletions(-)

diffs (130 lines):

diff -r 26473270b11c -r f395b2775b1c sys/arch/mips/mips/cache_octeon.c
--- a/sys/arch/mips/mips/cache_octeon.c Sat Jun 06 13:53:43 2020 +0000
+++ b/sys/arch/mips/mips/cache_octeon.c Sat Jun 06 14:30:44 2020 +0000
@@ -1,7 +1,7 @@
-/*     $NetBSD: cache_octeon.c,v 1.3 2019/04/13 21:39:46 maya Exp $    */
+/*     $NetBSD: cache_octeon.c,v 1.4 2020/06/06 14:30:44 simonb Exp $  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache_octeon.c,v 1.3 2019/04/13 21:39:46 maya Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache_octeon.c,v 1.4 2020/06/06 14:30:44 simonb Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -13,59 +13,55 @@
 #define        SYNC    __asm volatile("sync")
 
 #ifdef OCTEON_ICACHE_DEBUG
-int octeon_cache_debug;
+int octeon_cache_debug = 0;
+#define        ICACHE_DEBUG_PRINTF(x)                                          \
+       if (__predict_false(octeon_cache_debug != 0))                   \
+               printf x;
+#else
+#define        ICACHE_DEBUG_PRINTF(x)          /* nothing */
 #endif
 
+
 static inline void
 mips_synci(vaddr_t va)
 {
+
        __asm __volatile("synci 0(%0)" :: "r"(va));
 }
 
 void
 octeon_icache_sync_all(void)
 {
-#ifdef OCTEON_ICACHE_DEBUG
-       if (__predict_false(octeon_cache_debug != 0))
-               printf("%s\n", __func__);
-#endif
+
+       ICACHE_DEBUG_PRINTF(("%s\n", __func__));
        mips_synci(MIPS_KSEG0_START);
-//     cache_octeon_invalidate(CACHEOP_OCTEON_INV_ALL | CACHE_OCTEON_I);
        SYNC;
 }
 void
 octeon_icache_sync_range(register_t va, vsize_t size)
 {
-#ifdef OCTEON_ICACHE_DEBUG
-       if (__predict_false(octeon_cache_debug != 0))
-               printf("%s: va=%#"PRIxREGISTER", size=%#"PRIxVSIZE"\n",
-                   __func__, va, size);
-#endif
+
+       ICACHE_DEBUG_PRINTF(("%s: va=%#"PRIxREGISTER", size=%#"PRIxVSIZE"\n",
+           __func__, va, size));
        mips_synci(MIPS_KSEG0_START);
-//     cache_octeon_invalidate(CACHEOP_OCTEON_INV_ALL | CACHE_OCTEON_I);
        SYNC;
 }
 
 void
 octeon_icache_sync_range_index(vaddr_t va, vsize_t size)
 {
-#ifdef OCTEON_ICACHE_DEBUG
-       if (__predict_false(octeon_cache_debug != 0))
-               printf("%s: va=%#"PRIxVADDR", size=%#"PRIxVSIZE"\n",
-                   __func__, va, size);
-#endif
+
+       ICACHE_DEBUG_PRINTF(("%s: va=%#"PRIxVADDR", size=%#"PRIxVSIZE"\n",
+           __func__, va, size));
        mips_synci(MIPS_KSEG0_START);
-//     cache_octeon_invalidate(CACHEOP_OCTEON_INV_ALL | CACHE_OCTEON_I);
        SYNC;
 }
 
 void
 octeon_pdcache_inv_all(void)
 {
-#ifdef OCTEON_ICACHE_DEBUG
-       if (__predict_false(octeon_cache_debug != 0))
-               printf("%s\n", __func__);
-#endif
+
+       ICACHE_DEBUG_PRINTF(("%s\n", __func__));
        cache_octeon_invalidate(CACHEOP_OCTEON_INV_ALL | CACHE_OCTEON_D);
        SYNC;
 }
@@ -73,11 +69,9 @@
 void
 octeon_pdcache_inv_range(register_t va, vsize_t size)
 {
-#ifdef OCTEON_ICACHE_DEBUG
-       if (__predict_false(octeon_cache_debug != 0))
-               printf("%s: va=%#"PRIxREGISTER", size=%#"PRIxVSIZE"\n",
-                   __func__, va, size);
-#endif
+
+       ICACHE_DEBUG_PRINTF(("%s: va=%#"PRIxREGISTER", size=%#"PRIxVSIZE"\n",
+           __func__, va, size));
        cache_octeon_invalidate(CACHEOP_OCTEON_INV_ALL | CACHE_OCTEON_D);
        SYNC;
 }
@@ -85,11 +79,9 @@
 void
 octeon_pdcache_inv_range_index(vaddr_t va, vsize_t size)
 {
-#ifdef OCTEON_ICACHE_DEBUG
-       if (__predict_false(octeon_cache_debug != 0))
-               printf("%s: va=%#"PRIxVADDR", size=%#"PRIxVSIZE"\n",
-                   __func__, va, size);
-#endif
+
+       ICACHE_DEBUG_PRINTF(("%s: va=%#"PRIxVADDR", size=%#"PRIxVSIZE"\n",
+           __func__, va, size));
        cache_octeon_invalidate(CACHEOP_OCTEON_INV_ALL | CACHE_OCTEON_D);
        SYNC;
 }
@@ -98,6 +90,8 @@
 
 #ifdef OCTEON_ICACHE_DEBUG
 
+/* XXX does the following even make sense for Octeon II/III? */
+
 /* icache: 16KB, 2ways */
 
 #define        OCTEON_ICACHE_VA_WAY(_va)               (((_va) & __BITS(14, 13)) >> 13)