[src/trunk]: src/sys/arch/aarch64 Jazelle and T32EE are not part of ARMv8, fi...

[maxv <maxv%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/5dcb8386e26d
branches:  trunk
changeset: 968783:5dcb8386e26d
user:      maxv <maxv%NetBSD.org@localhost>
date:      Tue Jan 28 17:33:07 2020 +0000

description:
Jazelle and T32EE are not part of ARMv8, fix the bits to their real
meanings. No functional change.

diffstat:

 sys/arch/aarch64/aarch64/genassym.cf |  4 ++--
 sys/arch/aarch64/aarch64/locore.S    |  6 +++---
 sys/arch/aarch64/include/armreg.h    |  9 ++++-----
 3 files changed, 9 insertions(+), 10 deletions(-)

diffs (75 lines):

diff -r ab9d50a65b87 -r 5dcb8386e26d sys/arch/aarch64/aarch64/genassym.cf
--- a/sys/arch/aarch64/aarch64/genassym.cf      Tue Jan 28 17:23:30 2020 +0000
+++ b/sys/arch/aarch64/aarch64/genassym.cf      Tue Jan 28 17:33:07 2020 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.18 2020/01/08 17:38:41 ad Exp $
+# $NetBSD: genassym.cf,v 1.19 2020/01/28 17:33:07 maxv Exp $
 #-
 # Copyright (c) 2014 The NetBSD Foundation, Inc.
 # All rights reserved.
@@ -348,7 +348,7 @@
 define SCTLR_SA                SCTLR_SA
 define SCTLR_SA0               SCTLR_SA0
 define SCTLR_CP15BEN           SCTLR_CP15BEN
-define SCTLR_THEE              SCTLR_THEE
+define SCTLR_nAA               SCTLR_nAA
 define SCTLR_ITD               SCTLR_ITD
 define SCTLR_SED               SCTLR_SED
 define SCTLR_UMA               SCTLR_UMA
diff -r ab9d50a65b87 -r 5dcb8386e26d sys/arch/aarch64/aarch64/locore.S
--- a/sys/arch/aarch64/aarch64/locore.S Tue Jan 28 17:23:30 2020 +0000
+++ b/sys/arch/aarch64/aarch64/locore.S Tue Jan 28 17:33:07 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.53 2020/01/19 16:12:56 skrll Exp $        */
+/*     $NetBSD: locore.S,v 1.54 2020/01/28 17:33:07 maxv Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -38,7 +38,7 @@
 #include <aarch64/hypervisor.h>
 #include "assym.h"
 
-RCSID("$NetBSD: locore.S,v 1.53 2020/01/19 16:12:56 skrll Exp $")
+RCSID("$NetBSD: locore.S,v 1.54 2020/01/28 17:33:07 maxv Exp $")
 
 #ifdef AARCH64_DEVICE_MEM_STRONGLY_ORDERED
 #define        MAIR_DEVICE_MEM         MAIR_DEVICE_nGnRnE
@@ -1016,7 +1016,7 @@
            SCTLR_WXN |     /* Write permission implies Execute Never (W^X) */ \
            SCTLR_UMA |     /* EL0 Controls access to interrupt masks */ \
            SCTLR_ITD |     /* IT instruction disable */ \
-           SCTLR_THEE |    /* T32EE is not implemented */ \
+           SCTLR_nAA |     /* ? */ \
            SCTLR_CP15BEN | /* CP15 barrier enable */ \
            SCTLR_SA0 |     /* Enable EL0 stack alignment check */ \
            SCTLR_SA |      /* Enable SP alignment check */ \
diff -r ab9d50a65b87 -r 5dcb8386e26d sys/arch/aarch64/include/armreg.h
--- a/sys/arch/aarch64/include/armreg.h Tue Jan 28 17:23:30 2020 +0000
+++ b/sys/arch/aarch64/include/armreg.h Tue Jan 28 17:33:07 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.31 2020/01/28 17:23:30 maxv Exp $ */
+/* $NetBSD: armreg.h,v 1.32 2020/01/28 17:33:07 maxv Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -699,7 +699,7 @@
 #define        SCTLR_SA                __BIT(3)
 #define        SCTLR_SA0               __BIT(4)
 #define        SCTLR_CP15BEN           __BIT(5)
-#define        SCTLR_THEE              __BIT(6)
+#define        SCTLR_nAA               __BIT(6)
 #define        SCTLR_ITD               __BIT(7)
 #define        SCTLR_SED               __BIT(8)
 #define        SCTLR_UMA               __BIT(9)
@@ -743,9 +743,8 @@
 #define         SPSR_C                 __BIT(29)       // Carry
 #define         SPSR_V                 __BIT(28)       // oVerflow
 #define        SPSR_A32_Q              __BIT(27)       // A32: Overflow
-#define        SPSR_A32_J              __BIT(24)       // A32: Jazelle Mode
-#define        SPSR_A32_IT1            __BIT(23)       // A32: IT[1]
-#define        SPSR_A32_IT0            __BIT(22)       // A32: IT[0]
+#define        SPSR_A32_IT1            __BIT(26)       // A32: IT[1]
+#define        SPSR_A32_IT0            __BIT(25)       // A32: IT[0]
 #define        SPSR_SS                 __BIT(21)       // Software Step
 #define        SPSR_SS_SHIFT           21
 #define        SPSR_IL                 __BIT(20)       // Instruction Length