Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/aarch64 Do not try to initialize PMU if ID_AA64DFR0...
details: https://anonhg.NetBSD.org/src/rev/b160ce5d6fcb
branches: trunk
changeset: 984033:b160ce5d6fcb
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sat Jun 19 13:40:00 2021 +0000
description:
Do not try to initialize PMU if ID_AA64DFR0_EL1 reports a non-standard
PMU implementation.
diffstat:
sys/arch/aarch64/aarch64/cpu.c | 8 ++++++--
sys/arch/aarch64/include/armreg.h | 3 ++-
2 files changed, 8 insertions(+), 3 deletions(-)
diffs (46 lines):
diff -r d0aeec02bd6d -r b160ce5d6fcb sys/arch/aarch64/aarch64/cpu.c
--- a/sys/arch/aarch64/aarch64/cpu.c Sat Jun 19 13:38:21 2021 +0000
+++ b/sys/arch/aarch64/aarch64/cpu.c Sat Jun 19 13:40:00 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.59 2021/03/09 16:44:27 ryo Exp $ */
+/* $NetBSD: cpu.c,v 1.60 2021/06/19 13:40:00 jmcneill Exp $ */
/*
* Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.59 2021/03/09 16:44:27 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.60 2021/06/19 13:40:00 jmcneill Exp $");
#include "locators.h"
#include "opt_arm_debug.h"
@@ -486,6 +486,10 @@
/* Performance Monitors Extension not implemented. */
return;
}
+ if (pmuver == ID_AA64DFR0_EL1_PMUVER_IMPL) {
+ /* Non-standard Performance Monitors are not supported. */
+ return;
+ }
reg_pmcr_el0_write(PMCR_E | PMCR_C);
reg_pmcntenset_el0_write(PMCNTEN_C);
diff -r d0aeec02bd6d -r b160ce5d6fcb sys/arch/aarch64/include/armreg.h
--- a/sys/arch/aarch64/include/armreg.h Sat Jun 19 13:38:21 2021 +0000
+++ b/sys/arch/aarch64/include/armreg.h Sat Jun 19 13:40:00 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.56 2021/06/19 13:38:21 jmcneill Exp $ */
+/* $NetBSD: armreg.h,v 1.57 2021/06/19 13:40:00 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -248,6 +248,7 @@
#define ID_AA64DFR0_EL1_PMUVER_NONE 0
#define ID_AA64DFR0_EL1_PMUVER_V3 1
#define ID_AA64DFR0_EL1_PMUVER_NOV3 2
+#define ID_AA64DFR0_EL1_PMUVER_IMPL 15
#define ID_AA64DFR0_EL1_TRACEVER __BITS(4,7)
#define ID_AA64DFR0_EL1_TRACEVER_NONE 0
#define ID_AA64DFR0_EL1_TRACEVER_IMPL 1
Home |
Main Index |
Thread Index |
Old Index