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[xsrc/xorg]: xsrc/external/mit/libdrm/dist initial import of libdrm-2.4.107
details: https://anonhg.NetBSD.org/xsrc/rev/cbeab1481f94
branches: xorg
changeset: 10751:cbeab1481f94
user: mrg <mrg%NetBSD.org@localhost>
date: Sun Jul 11 00:27:20 2021 +0000
description:
initial import of libdrm-2.4.107
diffstat:
external/mit/libdrm/dist/README.rst | 18 +
external/mit/libdrm/dist/amdgpu/amdgpu.h | 1 +
external/mit/libdrm/dist/amdgpu/amdgpu_vamgr.c | 137 +++-
external/mit/libdrm/dist/core-symbols.txt | 2 +
external/mit/libdrm/dist/data/amdgpu.ids | 8 +
external/mit/libdrm/dist/gen_table_fourcc.py | 84 +++
external/mit/libdrm/dist/intel/i915_pciids.h | 21 +
external/mit/libdrm/dist/intel/intel_chipset.c | 1 +
external/mit/libdrm/dist/libkms/vmwgfx.c | 3 +
external/mit/libdrm/dist/meson.build | 11 +-
external/mit/libdrm/dist/nouveau/nouveau.c | 30 +-
external/mit/libdrm/dist/nouveau/private.h | 17 +-
external/mit/libdrm/dist/nouveau/pushbuf.c | 9 +-
external/mit/libdrm/dist/tests/amdgpu/amdgpu_test.c | 115 +++-
external/mit/libdrm/dist/tests/amdgpu/amdgpu_test.h | 44 +-
external/mit/libdrm/dist/tests/amdgpu/basic_tests.c | 61 +-
external/mit/libdrm/dist/tests/amdgpu/cs_tests.c | 7 +-
external/mit/libdrm/dist/tests/amdgpu/deadlock_tests.c | 18 +-
external/mit/libdrm/dist/tests/amdgpu/hotunplug_tests.c | 445 ++++++++++++++++
external/mit/libdrm/dist/tests/amdgpu/meson.build | 1 +
external/mit/libdrm/dist/tests/amdgpu/security_tests.c | 3 +-
external/mit/libdrm/dist/tests/amdgpu/syncobj_tests.c | 24 +-
external/mit/libdrm/dist/tests/amdgpu/vce_tests.c | 2 +-
external/mit/libdrm/dist/tests/amdgpu/vcn_tests.c | 2 +-
external/mit/libdrm/dist/tests/amdgpu/vm_tests.c | 9 +-
external/mit/libdrm/dist/tests/modetest/modetest.c | 75 +-
external/mit/libdrm/dist/xf86drm.c | 421 +++++++++++++++
external/mit/libdrm/dist/xf86drm.h | 11 +
external/mit/libdrm/dist/xf86drmMode.c | 7 +-
29 files changed, 1414 insertions(+), 173 deletions(-)
diffs (truncated from 2240 to 300 lines):
diff -r d7b6b09e4cf1 -r cbeab1481f94 external/mit/libdrm/dist/README.rst
--- a/external/mit/libdrm/dist/README.rst Sun Jul 11 00:08:36 2021 +0000
+++ b/external/mit/libdrm/dist/README.rst Sun Jul 11 00:27:20 2021 +0000
@@ -13,6 +13,24 @@
libdrm is a low-level library, typically used by graphics drivers such as
the Mesa drivers, the X drivers, libva and similar projects.
+Syncing with the Linux kernel headers
+-------------------------------------
+
+The library should be regularly updated to match the recent changes in the
+`include/uapi/drm/`.
+
+libdrm maintains a human-readable version for the token format modifier, with
+the simpler ones being extracted automatically from `drm_fourcc.h` header file
+with the help of a python script. This might not always possible, as some of
+the vendors require decoding/extracting them programmatically. For that
+reason one can enhance the current vendor functions to include/provide the
+newly added token formats, or, in case there's no such decoding
+function, to add one that performs the tasks of extracting them.
+
+For simpler format modifier tokens there's a script (gen_table_fourcc.py) that
+creates a static table, by going over `drm_fourcc.h` header file. The script
+could be further modified if it can't handle new (simpler) token format
+modifiers instead of the generated static table.
Compiling
---------
diff -r d7b6b09e4cf1 -r cbeab1481f94 external/mit/libdrm/dist/amdgpu/amdgpu.h
--- a/external/mit/libdrm/dist/amdgpu/amdgpu.h Sun Jul 11 00:08:36 2021 +0000
+++ b/external/mit/libdrm/dist/amdgpu/amdgpu.h Sun Jul 11 00:27:20 2021 +0000
@@ -1280,6 +1280,7 @@
*/
#define AMDGPU_VA_RANGE_32_BIT 0x1
#define AMDGPU_VA_RANGE_HIGH 0x2
+#define AMDGPU_VA_RANGE_REPLAYABLE 0x4
/**
* Allocate virtual address range
diff -r d7b6b09e4cf1 -r cbeab1481f94 external/mit/libdrm/dist/amdgpu/amdgpu_vamgr.c
--- a/external/mit/libdrm/dist/amdgpu/amdgpu_vamgr.c Sun Jul 11 00:08:36 2021 +0000
+++ b/external/mit/libdrm/dist/amdgpu/amdgpu_vamgr.c Sun Jul 11 00:27:20 2021 +0000
@@ -69,65 +69,99 @@
pthread_mutex_destroy(&mgr->bo_va_mutex);
}
-static drm_private uint64_t
+static drm_private int
+amdgpu_vamgr_subtract_hole(struct amdgpu_bo_va_hole *hole, uint64_t start_va,
+ uint64_t end_va)
+{
+ if (start_va > hole->offset && end_va - hole->offset < hole->size) {
+ struct amdgpu_bo_va_hole *n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
+ if (!n)
+ return -ENOMEM;
+
+ n->size = start_va - hole->offset;
+ n->offset = hole->offset;
+ list_add(&n->list, &hole->list);
+
+ hole->size -= (end_va - hole->offset);
+ hole->offset = end_va;
+ } else if (start_va > hole->offset) {
+ hole->size = start_va - hole->offset;
+ } else if (end_va - hole->offset < hole->size) {
+ hole->size -= (end_va - hole->offset);
+ hole->offset = end_va;
+ } else {
+ list_del(&hole->list);
+ free(hole);
+ }
+
+ return 0;
+}
+
+static drm_private int
amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size,
- uint64_t alignment, uint64_t base_required)
+ uint64_t alignment, uint64_t base_required,
+ bool search_from_top, uint64_t *va_out)
{
struct amdgpu_bo_va_hole *hole, *n;
- uint64_t offset = 0, waste = 0;
+ uint64_t offset = 0;
+ int ret;
alignment = MAX2(alignment, mgr->va_alignment);
size = ALIGN(size, mgr->va_alignment);
if (base_required % alignment)
- return AMDGPU_INVALID_VA_ADDRESS;
+ return -EINVAL;
pthread_mutex_lock(&mgr->bo_va_mutex);
- LIST_FOR_EACH_ENTRY_SAFE_REV(hole, n, &mgr->va_holes, list) {
- if (base_required) {
- if (hole->offset > base_required ||
- (hole->offset + hole->size) < (base_required + size))
- continue;
- waste = base_required - hole->offset;
- offset = base_required;
- } else {
- offset = hole->offset;
- waste = offset % alignment;
- waste = waste ? alignment - waste : 0;
- offset += waste;
- if (offset >= (hole->offset + hole->size)) {
- continue;
+ if (!search_from_top) {
+ LIST_FOR_EACH_ENTRY_SAFE_REV(hole, n, &mgr->va_holes, list) {
+ if (base_required) {
+ if (hole->offset > base_required ||
+ (hole->offset + hole->size) < (base_required + size))
+ continue;
+ offset = base_required;
+ } else {
+ uint64_t waste = hole->offset % alignment;
+ waste = waste ? alignment - waste : 0;
+ offset = hole->offset + waste;
+ if (offset >= (hole->offset + hole->size) ||
+ size > (hole->offset + hole->size) - offset) {
+ continue;
+ }
}
+ ret = amdgpu_vamgr_subtract_hole(hole, offset, offset + size);
+ pthread_mutex_unlock(&mgr->bo_va_mutex);
+ *va_out = offset;
+ return ret;
}
- if (!waste && hole->size == size) {
- offset = hole->offset;
- list_del(&hole->list);
- free(hole);
+ } else {
+ LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) {
+ if (base_required) {
+ if (hole->offset > base_required ||
+ (hole->offset + hole->size) < (base_required + size))
+ continue;
+ offset = base_required;
+ } else {
+ if (size > hole->size)
+ continue;
+
+ offset = hole->offset + hole->size - size;
+ offset -= offset % alignment;
+ if (offset < hole->offset) {
+ continue;
+ }
+ }
+
+ ret = amdgpu_vamgr_subtract_hole(hole, offset, offset + size);
pthread_mutex_unlock(&mgr->bo_va_mutex);
- return offset;
- }
- if ((hole->size - waste) > size) {
- if (waste) {
- n = calloc(1, sizeof(struct amdgpu_bo_va_hole));
- n->size = waste;
- n->offset = hole->offset;
- list_add(&n->list, &hole->list);
- }
- hole->size -= (size + waste);
- hole->offset += size + waste;
- pthread_mutex_unlock(&mgr->bo_va_mutex);
- return offset;
- }
- if ((hole->size - waste) == size) {
- hole->size = waste;
- pthread_mutex_unlock(&mgr->bo_va_mutex);
- return offset;
+ *va_out = offset;
+ return ret;
}
}
pthread_mutex_unlock(&mgr->bo_va_mutex);
- return AMDGPU_INVALID_VA_ADDRESS;
+ return -ENOMEM;
}
static drm_private void
@@ -196,6 +230,8 @@
uint64_t flags)
{
struct amdgpu_bo_va_mgr *vamgr;
+ bool search_from_top = !!(flags & AMDGPU_VA_RANGE_REPLAYABLE);
+ int ret;
/* Clear the flag when the high VA manager is not initialized */
if (flags & AMDGPU_VA_RANGE_HIGH && !dev->vamgr_high_32.va_max)
@@ -216,21 +252,22 @@
va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment);
size = ALIGN(size, vamgr->va_alignment);
- *va_base_allocated = amdgpu_vamgr_find_va(vamgr, size,
- va_base_alignment, va_base_required);
+ ret = amdgpu_vamgr_find_va(vamgr, size,
+ va_base_alignment, va_base_required,
+ search_from_top, va_base_allocated);
- if (!(flags & AMDGPU_VA_RANGE_32_BIT) &&
- (*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) {
+ if (!(flags & AMDGPU_VA_RANGE_32_BIT) && ret) {
/* fallback to 32bit address */
if (flags & AMDGPU_VA_RANGE_HIGH)
vamgr = &dev->vamgr_high_32;
else
vamgr = &dev->vamgr_32;
- *va_base_allocated = amdgpu_vamgr_find_va(vamgr, size,
- va_base_alignment, va_base_required);
+ ret = amdgpu_vamgr_find_va(vamgr, size,
+ va_base_alignment, va_base_required,
+ search_from_top, va_base_allocated);
}
- if (*va_base_allocated != AMDGPU_INVALID_VA_ADDRESS) {
+ if (!ret) {
struct amdgpu_va* va;
va = calloc(1, sizeof(struct amdgpu_va));
if(!va){
@@ -243,11 +280,9 @@
va->range = va_range_type;
va->vamgr = vamgr;
*va_range_handle = va;
- } else {
- return -EINVAL;
}
- return 0;
+ return ret;
}
drm_public int amdgpu_va_range_free(amdgpu_va_handle va_range_handle)
diff -r d7b6b09e4cf1 -r cbeab1481f94 external/mit/libdrm/dist/core-symbols.txt
--- a/external/mit/libdrm/dist/core-symbols.txt Sun Jul 11 00:08:36 2021 +0000
+++ b/external/mit/libdrm/dist/core-symbols.txt Sun Jul 11 00:27:20 2021 +0000
@@ -196,3 +196,5 @@
drmUnmapBufs
drmUpdateDrawableInfo
drmWaitVBlank
+drmGetFormatModifierName
+drmGetFormatModifierVendor
diff -r d7b6b09e4cf1 -r cbeab1481f94 external/mit/libdrm/dist/data/amdgpu.ids
--- a/external/mit/libdrm/dist/data/amdgpu.ids Sun Jul 11 00:08:36 2021 +0000
+++ b/external/mit/libdrm/dist/data/amdgpu.ids Sun Jul 11 00:27:20 2021 +0000
@@ -135,7 +135,9 @@
67C2, 01, AMD Radeon (TM) Pro V7350x2
67C2, 02, AMD Radeon (TM) Pro V7300X
67C4, 00, AMD Radeon (TM) Pro WX 7100 Graphics
+67C4, 80, AMD Radeon (TM) E9560/E9565 Graphics
67C7, 00, AMD Radeon (TM) Pro WX 5100 Graphics
+67C7, 80, AMD Radeon (TM) Pro E9390 Graphics
67C0, 00, AMD Radeon (TM) Pro WX 7100 Graphics
67D0, 01, AMD Radeon (TM) Pro V7350x2
67D0, 02, AMD Radeon (TM) Pro V7300X
@@ -271,9 +273,15 @@
7340, CF, Radeon RX 5300
7341, 00, AMD Radeon Pro W5500
7347, 00, AMD Radeon Pro W5500M
+73A3, 00, AMD Radeon PRO W6800
+73AF, C0, AMD Radeon RX 6900 XT
73BF, C0, AMD Radeon RX 6900 XT
73BF, C1, AMD Radeon RX 6800 XT
73BF, C3, AMD Radeon RX 6800
+73DF, C1, AMD Radeon RX 6700 XT
+73DF, C5, AMD Radeon RX 6700 XT
+73E1, 00, AMD Radeon PRO W6600M
+73E3, 00, AMD Radeon PRO W6600
9874, C4, AMD Radeon R7 Graphics
9874, C5, AMD Radeon R6 Graphics
9874, C6, AMD Radeon R6 Graphics
diff -r d7b6b09e4cf1 -r cbeab1481f94 external/mit/libdrm/dist/gen_table_fourcc.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/external/mit/libdrm/dist/gen_table_fourcc.py Sun Jul 11 00:27:20 2021 +0000
@@ -0,0 +1,84 @@
+#!/usr/bin/env python3
+
+# Copyright 2021 Collabora, Ltd.
+#
+# Permission is hereby granted, free of charge, to any person obtaining
+# a copy of this software and associated documentation files (the
+# "Software"), to deal in the Software without restriction, including
+# without limitation the rights to use, copy, modify, merge, publish,
+# distribute, sublicense, and/or sell copies of the Software, and to
+# permit persons to whom the Software is furnished to do so, subject to
+# the following conditions:
+#
+# The above copyright notice and this permission notice (including the
+# next paragraph) shall be included in all copies or substantial
+# portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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