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[xsrc/trunk]: xsrc/external/mit/libdrm/include avoid 'visibility' attribute o...
details: https://anonhg.NetBSD.org/xsrc/rev/c3c3d8fa91d2
branches: trunk
changeset: 10759:c3c3d8fa91d2
user: mrg <mrg%NetBSD.org@localhost>
date: Sun Jul 11 00:41:13 2021 +0000
description:
avoid 'visibility' attribute on static functions.
diffstat:
external/mit/libdrm/dist/amdgpu/amdgpu_vamgr.c | 4 +-
external/mit/libdrm/include/generated_static_table_fourcc.h | 48 +++++++++++++
2 files changed, 50 insertions(+), 2 deletions(-)
diffs (73 lines):
diff -r 126d7703ff84 -r c3c3d8fa91d2 external/mit/libdrm/dist/amdgpu/amdgpu_vamgr.c
--- a/external/mit/libdrm/dist/amdgpu/amdgpu_vamgr.c Sun Jul 11 00:31:53 2021 +0000
+++ b/external/mit/libdrm/dist/amdgpu/amdgpu_vamgr.c Sun Jul 11 00:41:13 2021 +0000
@@ -69,7 +69,7 @@
pthread_mutex_destroy(&mgr->bo_va_mutex);
}
-static drm_private int
+static int
amdgpu_vamgr_subtract_hole(struct amdgpu_bo_va_hole *hole, uint64_t start_va,
uint64_t end_va)
{
@@ -97,7 +97,7 @@
return 0;
}
-static drm_private int
+static int
amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size,
uint64_t alignment, uint64_t base_required,
bool search_from_top, uint64_t *va_out)
diff -r 126d7703ff84 -r c3c3d8fa91d2 external/mit/libdrm/include/generated_static_table_fourcc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/external/mit/libdrm/include/generated_static_table_fourcc.h Sun Jul 11 00:41:13 2021 +0000
@@ -0,0 +1,48 @@
+/* AUTOMATICALLY GENERATED by gen_table_fourcc.py. You should modify
+ that script instead of adding here entries manually! */
+static const struct drmFormatModifierInfo drm_format_modifier_table[] = {
+ { DRM_MODIFIER_INVALID(NONE, INVALID_MODIFIER) },
+ { DRM_MODIFIER_LINEAR(NONE, LINEAR) },
+ { DRM_MODIFIER_INTEL(X_TILED, X_TILED) },
+ { DRM_MODIFIER_INTEL(Y_TILED, Y_TILED) },
+ { DRM_MODIFIER_INTEL(Yf_TILED, Yf_TILED) },
+ { DRM_MODIFIER_INTEL(Y_TILED_CCS, Y_TILED_CCS) },
+ { DRM_MODIFIER_INTEL(Yf_TILED_CCS, Yf_TILED_CCS) },
+ { DRM_MODIFIER_INTEL(Y_TILED_GEN12_RC_CCS, Y_TILED_GEN12_RC_CCS) },
+ { DRM_MODIFIER_INTEL(Y_TILED_GEN12_MC_CCS, Y_TILED_GEN12_MC_CCS) },
+ { DRM_MODIFIER(SAMSUNG, 64_32_TILE, 64_32_TILE) },
+ { DRM_MODIFIER(SAMSUNG, 16_16_TILE, 16_16_TILE) },
+ { DRM_MODIFIER(QCOM, COMPRESSED, COMPRESSED) },
+ { DRM_MODIFIER(VIVANTE, TILED, TILED) },
+ { DRM_MODIFIER(VIVANTE, SUPER_TILED, SUPER_TILED) },
+ { DRM_MODIFIER(VIVANTE, SPLIT_TILED, SPLIT_TILED) },
+ { DRM_MODIFIER(VIVANTE, SPLIT_SUPER_TILED, SPLIT_SUPER_TILED) },
+ { DRM_MODIFIER(NVIDIA, TEGRA_TILED, TEGRA_TILED) },
+ { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_ONE_GOB, 16BX2_BLOCK_ONE_GOB) },
+ { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_TWO_GOB, 16BX2_BLOCK_TWO_GOB) },
+ { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_FOUR_GOB, 16BX2_BLOCK_FOUR_GOB) },
+ { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_EIGHT_GOB, 16BX2_BLOCK_EIGHT_GOB) },
+ { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_SIXTEEN_GOB, 16BX2_BLOCK_SIXTEEN_GOB) },
+ { DRM_MODIFIER(NVIDIA, 16BX2_BLOCK_THIRTYTWO_GOB, 16BX2_BLOCK_THIRTYTWO_GOB) },
+ { DRM_MODIFIER(BROADCOM, VC4_T_TILED, VC4_T_TILED) },
+ { DRM_MODIFIER(BROADCOM, SAND32, SAND32) },
+ { DRM_MODIFIER(BROADCOM, SAND64, SAND64) },
+ { DRM_MODIFIER(BROADCOM, SAND128, SAND128) },
+ { DRM_MODIFIER(BROADCOM, SAND256, SAND256) },
+ { DRM_MODIFIER(BROADCOM, UIF, UIF) },
+ { DRM_MODIFIER(ARM, 16X16_BLOCK_U_INTERLEAVED, 16X16_BLOCK_U_INTERLEAVED) },
+ { DRM_MODIFIER(ALLWINNER, TILED, TILED) },
+};
+static const struct drmFormatModifierVendorInfo drm_format_modifier_vendor_table[] = {
+ { DRM_FORMAT_MOD_VENDOR_NONE, "NONE" },
+ { DRM_FORMAT_MOD_VENDOR_INTEL, "INTEL" },
+ { DRM_FORMAT_MOD_VENDOR_AMD, "AMD" },
+ { DRM_FORMAT_MOD_VENDOR_NVIDIA, "NVIDIA" },
+ { DRM_FORMAT_MOD_VENDOR_SAMSUNG, "SAMSUNG" },
+ { DRM_FORMAT_MOD_VENDOR_QCOM, "QCOM" },
+ { DRM_FORMAT_MOD_VENDOR_VIVANTE, "VIVANTE" },
+ { DRM_FORMAT_MOD_VENDOR_BROADCOM, "BROADCOM" },
+ { DRM_FORMAT_MOD_VENDOR_ARM, "ARM" },
+ { DRM_FORMAT_MOD_VENDOR_ALLWINNER, "ALLWINNER" },
+ { DRM_FORMAT_MOD_VENDOR_AMLOGIC, "AMLOGIC" },
+};
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