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[src/trunk]: src/sys/arch/arm/cortex Trailing whitespace
details: https://anonhg.NetBSD.org/src/rev/fec00a6c1dbe
branches: trunk
changeset: 988203:fec00a6c1dbe
user: skrll <skrll%NetBSD.org@localhost>
date: Sat Oct 02 20:52:09 2021 +0000
description:
Trailing whitespace
diffstat:
sys/arch/arm/cortex/a9tmr_reg.h | 4 ++--
sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S | 4 ++--
sys/arch/arm/cortex/gicv3.c | 6 +++---
sys/arch/arm/cortex/pl310.c | 6 +++---
4 files changed, 10 insertions(+), 10 deletions(-)
diffs (93 lines):
diff -r c1f495a86919 -r fec00a6c1dbe sys/arch/arm/cortex/a9tmr_reg.h
--- a/sys/arch/arm/cortex/a9tmr_reg.h Sat Oct 02 20:45:34 2021 +0000
+++ b/sys/arch/arm/cortex/a9tmr_reg.h Sat Oct 02 20:52:09 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: a9tmr_reg.h,v 1.2 2019/07/27 07:02:09 skrll Exp $ */
+/* $NetBSD: a9tmr_reg.h,v 1.3 2021/10/02 20:52:09 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -87,7 +87,7 @@
#define TMR_GBL_CTL_PRESCALER __BIT(15,8)
#define TMR_GBL_CTL_AUTO_INC __BIT(3) // Auto Increment is enabled
#define TMR_GBL_CTL_INT_ENABLE __BIT(2) // [banked] INT 27 is enabled
-#define TMR_GBL_CTL_CMP_ENABLE __BIT(1) // [banked]
+#define TMR_GBL_CTL_CMP_ENABLE __BIT(1) // [banked]
#define TMR_GBL_CTL_ENABLE __BIT(0)
#endif /* !_ARM_CORTEX_A9TMR_REG_H_ */
diff -r c1f495a86919 -r fec00a6c1dbe sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S
--- a/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S Sat Oct 02 20:45:34 2021 +0000
+++ b/sys/arch/arm/cortex/cpu_in_cksum_asm_neon.S Sat Oct 02 20:52:09 2021 +0000
@@ -29,7 +29,7 @@
#include <machine/asm.h>
-RCSID("$NetBSD: cpu_in_cksum_asm_neon.S,v 1.3 2012/12/22 18:58:29 matt Exp $")
+RCSID("$NetBSD: cpu_in_cksum_asm_neon.S,v 1.4 2021/10/02 20:52:09 skrll Exp $")
/*
* uint32_t
@@ -52,7 +52,7 @@
* Normally the lower addressed is in d6 but in this case we want to
* reverse it since we might only have a single dword and the final
* fold will want the dword to trim in d7 so put the first dword in
- * d7 until we know we are going to read more than one.
+ * d7 until we know we are going to read more than one.
*/
veor d6, d6, d6 /* clear second dword */
vld1.64 {d7}, [ip:64]! /* load first dword */
diff -r c1f495a86919 -r fec00a6c1dbe sys/arch/arm/cortex/gicv3.c
--- a/sys/arch/arm/cortex/gicv3.c Sat Oct 02 20:45:34 2021 +0000
+++ b/sys/arch/arm/cortex/gicv3.c Sat Oct 02 20:52:09 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gicv3.c,v 1.48 2021/09/26 13:38:50 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.49 2021/10/02 20:52:09 skrll Exp $ */
/*-
* Copyright (c) 2018 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -32,7 +32,7 @@
#define _INTR_PRIVATE
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.48 2021/09/26 13:38:50 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.49 2021/10/02 20:52:09 skrll Exp $");
#include <sys/param.h>
#include <sys/kernel.h>
@@ -837,7 +837,7 @@
/*
* If we see fewer PMR bits than IPRIORITYRn bits here, it means
* we have a secure view of IPRIORITYRn (this is not supposed to
- * happen!).
+ * happen!).
*/
if (pmrbits < pribits) {
aprint_verbose_dev(sc->sc_dev,
diff -r c1f495a86919 -r fec00a6c1dbe sys/arch/arm/cortex/pl310.c
--- a/sys/arch/arm/cortex/pl310.c Sat Oct 02 20:45:34 2021 +0000
+++ b/sys/arch/arm/cortex/pl310.c Sat Oct 02 20:52:09 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pl310.c,v 1.19 2019/01/19 20:52:26 jmcneill Exp $ */
+/* $NetBSD: pl310.c,v 1.20 2021/10/02 20:52:09 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.19 2019/01/19 20:52:26 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pl310.c,v 1.20 2021/10/02 20:52:09 skrll Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -157,7 +157,7 @@
mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);
- bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh,
+ bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh,
off, L2CC_SIZE, &sc->sc_memh);
uint32_t id = arml2cc_read_4(sc, L2C_CACHE_ID);
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