[src/trunk]: src/sys/arch/arm/acpi Add CPU performance counter support

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/3dc86b3ca9f2
branches:  trunk
changeset: 995083:3dc86b3ca9f2
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Wed Dec 05 22:42:55 2018 +0000

description:
Add CPU performance counter support

diffstat:

 sys/arch/arm/acpi/cpu_acpi.c |  112 ++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 110 insertions(+), 2 deletions(-)

diffs (149 lines):

diff -r 70c1ab9ccb66 -r 3dc86b3ca9f2 sys/arch/arm/acpi/cpu_acpi.c
--- a/sys/arch/arm/acpi/cpu_acpi.c      Wed Dec 05 22:42:27 2018 +0000
+++ b/sys/arch/arm/acpi/cpu_acpi.c      Wed Dec 05 22:42:55 2018 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_acpi.c,v 1.4 2018/10/19 11:11:03 jmcneill Exp $ */
+/* $NetBSD: cpu_acpi.c,v 1.5 2018/12/05 22:42:55 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
@@ -29,13 +29,17 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include "tprof.h"
+
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_acpi.c,v 1.4 2018/10/19 11:11:03 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_acpi.c,v 1.5 2018/12/05 22:42:55 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
+#include <sys/interrupt.h>
+#include <sys/kcpuset.h>
 
 #include <dev/acpi/acpireg.h>
 #include <dev/acpi/acpivar.h>
@@ -47,11 +51,19 @@
 
 #include <arm/arm/psci.h>
 
+#if NTPROF > 0
+#include <dev/tprof/tprof_armv8.h>
+#endif
+
 extern struct cpu_info cpu_info_store[];
 
 static int     cpu_acpi_match(device_t, cfdata_t, void *);
 static void    cpu_acpi_attach(device_t, device_t, void *);
 
+#if NTPROF > 0
+static void    cpu_acpi_tprof_init(device_t);
+#endif
+
 CFATTACH_DECL_NEW(cpu_acpi, 0, cpu_acpi_match, cpu_acpi_attach, NULL, NULL);
 
 static register_t
@@ -111,4 +123,100 @@
 
        /* Attach the CPU */
        cpu_attach(self, mpidr);
+
+#if NTPROF > 0
+       if (cpu_mpidr_aff_read() == mpidr)
+               config_interrupts(self, cpu_acpi_tprof_init);
+#endif
 }
+
+#if NTPROF > 0
+static struct cpu_info *
+cpu_acpi_find_processor(UINT32 uid)
+{
+       CPU_INFO_ITERATOR cii;
+       struct cpu_info *ci;
+
+       for (CPU_INFO_FOREACH(cii, ci)) {
+               if (ci->ci_acpiid == uid)
+                       return ci;
+       }
+
+       return NULL;
+}
+
+static ACPI_STATUS
+cpu_acpi_tprof_intr_establish(ACPI_SUBTABLE_HEADER *hdrp, void *aux)
+{
+       device_t dev = aux;
+       ACPI_MADT_GENERIC_INTERRUPT *gicc;
+       struct cpu_info *ci;
+       char xname[16];
+       kcpuset_t *set;
+       int error;
+       void *ih;
+
+       if (hdrp->Type != ACPI_MADT_TYPE_GENERIC_INTERRUPT)
+               return AE_OK;
+
+       gicc = (ACPI_MADT_GENERIC_INTERRUPT *)hdrp;
+       if ((gicc->Flags & ACPI_MADT_ENABLED) == 0)
+               return AE_OK;
+
+       const bool cpu_primary_p = cpu_mpidr_aff_read() == gicc->ArmMpidr;
+       const bool intr_ppi_p = gicc->PerformanceInterrupt < 32;
+       const int type = (gicc->Flags & ACPI_MADT_PERFORMANCE_IRQ_MODE) ? IST_EDGE : IST_LEVEL;
+
+       if (intr_ppi_p && !cpu_primary_p)
+               return AE_OK;
+
+       ci = cpu_acpi_find_processor(gicc->Uid);
+       if (ci == NULL) {
+               aprint_error_dev(dev, "couldn't find processor %#x\n", gicc->Uid);
+               return AE_OK;
+       }
+
+       if (intr_ppi_p) {
+               strlcpy(xname, "pmu", sizeof(xname));
+       } else {
+               snprintf(xname, sizeof(xname), "pmu %s", cpu_name(ci));
+       }
+
+       ih = intr_establish_xname(gicc->PerformanceInterrupt, IPL_HIGH, type | IST_MPSAFE,
+           armv8_pmu_intr, NULL, xname);
+       if (ih == NULL) {
+               aprint_error_dev(dev, "couldn't establish %s interrupt\n", xname);
+               return AE_OK;
+       }
+
+       if (!intr_ppi_p) {
+               kcpuset_create(&set, true);
+               kcpuset_set(set, cpu_index(ci));
+               error = interrupt_distribute(ih, set, NULL);
+               kcpuset_destroy(set);
+
+               if (error) {
+                       aprint_error_dev(dev, "failed to distribute %s interrupt: %d\n",
+                           xname, error);
+                       return AE_OK;
+               }
+       }
+
+       aprint_normal("%s: PMU interrupting on irq %d\n", cpu_name(ci), gicc->PerformanceInterrupt);
+
+       return AE_OK;
+}
+
+static void
+cpu_acpi_tprof_init(device_t self)
+{
+       armv8_pmu_init();
+
+       if (acpi_madt_map() != AE_OK) {
+               aprint_error_dev(self, "failed to map MADT, performance counters not available\n");
+               return;
+       }
+       acpi_madt_walk(cpu_acpi_tprof_intr_establish, self);
+       acpi_madt_unmap();
+}
+#endif