[src/trunk]: src/sys/arch/x86/include Add TSX_FORCE_ABORT related definitions.

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/28fbd2697d95
branches:  trunk
changeset: 997565:28fbd2697d95
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Wed Mar 13 05:22:07 2019 +0000

description:
Add TSX_FORCE_ABORT related definitions.

diffstat:

 sys/arch/x86/include/specialreg.h |  9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)

diffs (38 lines):

diff -r 72a191a3ea4e -r 28fbd2697d95 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Tue Mar 12 23:52:46 2019 +0000
+++ b/sys/arch/x86/include/specialreg.h Wed Mar 13 05:22:07 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.142 2019/03/09 08:42:26 maxv Exp $    */
+/*     $NetBSD: specialreg.h,v 1.143 2019/03/13 05:22:07 msaitoh Exp $ */
 
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
@@ -426,6 +426,7 @@
 /* %edx */
 #define CPUID_SEF_AVX512_4VNNIW        __BIT(2)
 #define CPUID_SEF_AVX512_4FMAPS        __BIT(3)
+#define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */
 #define CPUID_SEF_IBRS         __BIT(26) /* IBRS / IBPB Speculation Control */
 #define CPUID_SEF_STIBP                __BIT(27) /* STIBP Speculation Control */
 #define CPUID_SEF_L1D_FLUSH    __BIT(28) /* IA32_FLUSH_CMD MSR */
@@ -435,7 +436,8 @@
 
 #define CPUID_SEF_FLAGS2       "\20" \
                                "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
-                                       "\33" "IBRS"    "\34" "STIBP"   \
+                       "\16" "TSX_FORCE_ABORT"                         \
+       "\33" "IBRS"    "\34" "STIBP"                                   \
        "\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP"        "\40" "SSBD"
 
 /*
@@ -745,8 +747,9 @@
 #define        IA32_ARCH_RSBA          0x04
 #define        IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08
 #define        IA32_ARCH_SSB_NO        0x10
-#define MSR_IA32_FLUSH_CMD 0x10b
+#define MSR_IA32_FLUSH_CMD     0x10b
 #define        IA32_FLUSH_CMD_L1D_FLUSH 0x01
+#define MSR_TSX_FORCE_ABORT    0x10f
 #define MSR_BBL_CR_ADDR                0x116   /* PII+ only */
 #define MSR_BBL_CR_DECC                0x118   /* PII+ only */
 #define MSR_BBL_CR_CTL         0x119   /* PII+ only */