[src/netbsd-9]: src/sys/arch/emips/emips Pull up following revision(s) (reque...

[martin <martin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/5de9ef566482
branches:  netbsd-9
changeset: 1001291:5de9ef566482
user:      martin <martin%NetBSD.org@localhost>
date:      Sat Dec 14 12:22:43 2019 +0000

description:
Pull up following revision(s) (requested by tsutsui in ticket #549):

        sys/arch/emips/emips/interrupt.c: revision 1.7
        sys/arch/emips/emips/interrupt.c: revision 1.8

Fix incorrect argument order of cpu_intr(), slipped in rev 1.2.

Pointed out by maya@ in PR/45080.

Should be pulled up to netbsd-9.

 -

Fix a longstanding "freeze right after enabling interrupt" problem.

With this fix, finally NetBSD/emips on Giano is fully functional.
See PR/45080 for more details.

Should be pulled up to netbsd-9.

diffstat:

 sys/arch/emips/emips/interrupt.c |  27 ++++++++++++++++++++++++---
 1 files changed, 24 insertions(+), 3 deletions(-)

diffs (61 lines):

diff -r fc537067a105 -r 5de9ef566482 sys/arch/emips/emips/interrupt.c
--- a/sys/arch/emips/emips/interrupt.c  Thu Dec 12 21:02:18 2019 +0000
+++ b/sys/arch/emips/emips/interrupt.c  Sat Dec 14 12:22:43 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: interrupt.c,v 1.6 2016/07/11 16:18:56 matt Exp $       */
+/*     $NetBSD: interrupt.c,v 1.6.22.1 2019/12/14 12:22:43 martin Exp $        */
 
 /*-
  * Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.6 2016/07/11 16:18:56 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: interrupt.c,v 1.6.22.1 2019/12/14 12:22:43 martin Exp $");
 
 #include <sys/param.h>
 #include <sys/device.h>
@@ -95,13 +95,26 @@
  * emips uses one line for all I/O interrupts (0x8000).
  */
 void
-cpu_intr(int ppl, uint32_t status, vaddr_t pc)
+cpu_intr(int ppl, vaddr_t pc, uint32_t status)
 {
        uint32_t ipending;
        int ipl;
 
        curcpu()->ci_data.cpu_nintr++;
 
+#if 0
+       /*
+        * According to Giano simulator sources (Cpus/mips_cpu.cpp),
+        * interrupt register bits in CAUSE register are updated
+        * only when the exception is triggered. This means checking
+        * CAUSE register via splintr() in a while loop in this
+        * interrupt handler doesn't work as expected on Giano.
+        *
+        * I don't know whether the real FPGA eMIPS has the same
+        * design as the Giano simulator, but for now I'd like to
+        * choose 'call only one handler per each interrupt' strategy,
+        * as the original NetBSD/emips implementation.
+        */
        while (ppl < (ipl = splintr(&ipending))) {
                splx(ipl);
                /* device interrupts */
@@ -110,6 +123,14 @@
                }
                (void)splhigh();
        }
+#else
+       ipl = splintr(&ipending);
+       __USE(ipl);
+       /* device interrupts */
+       if (ipending & MIPS_INT_MASK_5) {
+               (*platform.iointr)(status, pc, ipending);
+       }
+#endif
 }
 
 /*