[src/netbsd-9]: src/sys/arch/mips/mips Pull up following revision(s) (request...

[martin <martin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/cf7e899011a2
branches:  netbsd-9
changeset: 1001823:cf7e899011a2
user:      martin <martin%NetBSD.org@localhost>
date:      Sat Jun 20 16:35:02 2020 +0000

description:
Pull up following revision(s) (requested by tsutsui in ticket #964):

        sys/arch/mips/mips/cache.c: revision 1.67

Use 32 byte cacheline ops (not 16 byte ones) for R5000 picache.  PR/55138

Commented "I think this is bad copy&paste" from skrll@.

No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.

diffstat:

 sys/arch/mips/mips/cache.c |  8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diffs (32 lines):

diff -r 14f0397493b1 -r cf7e899011a2 sys/arch/mips/mips/cache.c
--- a/sys/arch/mips/mips/cache.c        Sat Jun 20 16:22:57 2020 +0000
+++ b/sys/arch/mips/mips/cache.c        Sat Jun 20 16:35:02 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.c,v 1.60 2018/09/03 16:29:26 riastradh Exp $     */
+/*     $NetBSD: cache.c,v 1.60.4.1 2020/06/20 16:35:02 martin Exp $    */
 
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.60 2018/09/03 16:29:26 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.60.4.1 2020/06/20 16:35:02 martin Exp $");
 
 #include "opt_cputype.h"
 #include "opt_mips_cache.h"
@@ -494,11 +494,11 @@
                case 32:
                        /* used internally by mipsNN_picache_sync_range */
                        mco->mco_intern_icache_sync_range =
-                           cache_r4k_icache_hit_inv_16;
+                           cache_r4k_icache_hit_inv_32;
 
                        /* used internally by mipsNN_picache_sync_range_index */
                        mco->mco_intern_icache_sync_range_index =
-                           cache_r4k_icache_index_inv_16;
+                           cache_r4k_icache_index_inv_32;
                        break;
 
                default: