Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/netbsd-9]: src/sys/dev Pull up following revision(s) (requested by msait...
details: https://anonhg.NetBSD.org/src/rev/2ec676c73199
branches: netbsd-9
changeset: 1002004:2ec676c73199
user: martin <martin%NetBSD.org@localhost>
date: Wed Sep 23 08:46:54 2020 +0000
description:
Pull up following revision(s) (requested by msaitoh in ticket #1093):
sys/dev/pci/if_wmreg.h: revision 1.120
sys/dev/pci/if_wmvar.h: revision 1.46
sys/dev/pci/if_wm.c: revision 1.686
sys/dev/pci/if_wm.c: revision 1.687
sys/dev/mii/inbmphyreg.h: revision 1.20
sys/dev/pci/if_wm.c: revision 1.688
sys/dev/pci/if_wm.c: revision 1.689
s/ressource/resource/. Found by knakahara.
Add new flag named WM_F_CRC_STRIP and use it. No functional change.
This change also sets the RCTL_SECRC bit on I211 but it doesn't change
the behavior because I211 always strips CRC like I35[04] and I210.
Add a workaround for jumbo frame on PCH2 and newer. Tested by chs@.
- Add wm_lv_jumbo_workaround_ich8lan() and use it. From FreeBSD.
XXX For KUMCTRLSTA_OFFSET_HD_CTRL register modification, it's doubtful.
FreeBSD and Linux do the same thing that they set the same value on both
jumbo frame's enable case and the disable case. It seems the default value
is 0x0b0c and it's not changed on the enable case, so it might be a bug
on the enable case or the modification is not required.
- Rename I219_UNKNOWN1 to I82579_UNKNOWN1.
Use 12K for packet buffer for jumbo frame on PCH2 and newer.
XXX Note that Linux Use 14K.
diffstat:
sys/dev/mii/inbmphyreg.h | 7 +-
sys/dev/pci/if_wm.c | 284 ++++++++++++++++++++++++++++++++++++++++------
sys/dev/pci/if_wmreg.h | 5 +-
sys/dev/pci/if_wmvar.h | 5 +-
4 files changed, 255 insertions(+), 46 deletions(-)
diffs (truncated from 550 to 300 lines):
diff -r e7ce664b21a6 -r 2ec676c73199 sys/dev/mii/inbmphyreg.h
--- a/sys/dev/mii/inbmphyreg.h Tue Sep 22 18:43:22 2020 +0000
+++ b/sys/dev/mii/inbmphyreg.h Wed Sep 23 08:46:54 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: inbmphyreg.h,v 1.18 2019/01/31 15:30:23 msaitoh Exp $ */
+/* $NetBSD: inbmphyreg.h,v 1.18.4.1 2020/09/23 08:46:54 martin Exp $ */
/*******************************************************************************
Copyright (c) 2001-2015, Intel Corporation
All rights reserved.
@@ -136,6 +136,8 @@
#define BM_PORT_GEN_CFG BME1000_REG(BM_PORT_CTRL_PAGE, 17)
+#define I82579_DFT_CTRL BME1000_REG(BM_PORT_CTRL_PAGE, 20)
+
#define CV_SMB_CTRL BME1000_REG(BM_PORT_CTRL_PAGE, 23)
#define CV_SMB_CTRL_FORCE_SMBUS __BIT(0)
@@ -180,7 +182,8 @@
#define HV_MUX_DATA_CTRL_FORCE_SPEED (1 << 2)
#define HV_MUX_DATA_CTRL_GEN_TO_MAC (1 << 10)
-#define I219_UNKNOWN1 BME1000_REG(776, 20)
+#define I82579_UNKNOWN1 BME1000_REG(776, 20)
+#define I82579_TX_PTR_GAP 0x1f
#define I218_ULP_CONFIG1 BME1000_REG(779, 16)
#define I218_ULP_CONFIG1_START __BIT(0)
diff -r e7ce664b21a6 -r 2ec676c73199 sys/dev/pci/if_wm.c
--- a/sys/dev/pci/if_wm.c Tue Sep 22 18:43:22 2020 +0000
+++ b/sys/dev/pci/if_wm.c Wed Sep 23 08:46:54 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.645.2.6 2020/08/05 15:14:18 martin Exp $ */
+/* $NetBSD: if_wm.c,v 1.645.2.7 2020/09/23 08:46:54 martin Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -82,7 +82,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.645.2.6 2020/08/05 15:14:18 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.645.2.7 2020/09/23 08:46:54 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_net_mpsafe.h"
@@ -1015,6 +1015,8 @@
static void wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
static int wm_hv_phy_workarounds_ich8lan(struct wm_softc *);
static void wm_copy_rx_addrs_to_phy_ich8lan(struct wm_softc *);
+static void wm_copy_rx_addrs_to_phy_ich8lan_locked(struct wm_softc *);
+static int wm_lv_jumbo_workaround_ich8lan(struct wm_softc *, bool);
static int wm_lv_phy_workarounds_ich8lan(struct wm_softc *);
static int wm_k1_workaround_lpt_lp(struct wm_softc *, bool);
static int wm_k1_gig_workaround_hv(struct wm_softc *, int);
@@ -2885,6 +2887,14 @@
sc->sc_flags |= WM_F_EEE;
}
+ /*
+ * The I350 has a bug where it always strips the CRC whether
+ * asked to or not. So ask for stripped CRC here and cope in rxeof
+ */
+ if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
+ || (sc->sc_type == WM_T_I210) || (sc->sc_type == WM_T_I211))
+ sc->sc_flags |= WM_F_CRC_STRIP;
+
/* Set device properties (macflags) */
prop_dictionary_set_uint32(dict, "macflags", sc->sc_flags);
@@ -3791,7 +3801,7 @@
struct ether_multistep step;
bus_addr_t mta_reg;
uint32_t hash, reg, bit;
- int i, size, ralmax;
+ int i, size, ralmax, rv;
DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
device_xname(sc->sc_dev), __func__));
@@ -3917,6 +3927,17 @@
sc->sc_rctl |= RCTL_MPE;
setit:
+ if (sc->sc_type >= WM_T_PCH2) {
+ if (((ec->ec_capabilities & ETHERCAP_JUMBO_MTU) != 0)
+ && (ifp->if_mtu > ETHERMTU))
+ rv = wm_lv_jumbo_workaround_ich8lan(sc, true);
+ else
+ rv = wm_lv_jumbo_workaround_ich8lan(sc, false);
+ if (rv != 0)
+ device_printf(sc->sc_dev,
+ "Failed to do workaround for jumbo frame.\n");
+ }
+
CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl);
}
@@ -4849,7 +4870,8 @@
case WM_T_PCH_LPT:
case WM_T_PCH_SPT:
case WM_T_PCH_CNP:
- sc->sc_pba = PBA_26K;
+ sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 1500 ?
+ PBA_12K : PBA_26K;
break;
default:
sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
@@ -6308,12 +6330,7 @@
if (sc->sc_type == WM_T_82574)
sc->sc_rctl |= RCTL_DTYP_ONEBUF;
- /*
- * The I350 has a bug where it always strips the CRC whether
- * asked to or not. So ask for stripped CRC here and cope in rxeof
- */
- if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)
- || (sc->sc_type == WM_T_I210))
+ if ((sc->sc_flags & WM_F_CRC_STRIP) != 0)
sc->sc_rctl |= RCTL_SECRC;
if (((ec->ec_capabilities & ETHERCAP_JUMBO_MTU) != 0)
@@ -9069,17 +9086,16 @@
/*
* Okay, we have the entire packet now. The chip is
- * configured to include the FCS except I350 and I21[01]
- * (not all chips can be configured to strip it),
- * so we need to trim it.
+ * configured to include the FCS except I35[05], I21[01].
+ * (not all chips can be configured to strip it), so we need
+ * to trim it. Those chips have an eratta, the RCTL_SECRC bit
+ * in RCTL register is always set, so we don't trim it.
+ * PCH2 and newer chip also not include FCS when jumbo
+ * frame is used to do workaround an errata.
* May need to adjust length of previous mbuf in the
* chain if the current mbuf is too short.
- * For an eratta, the RCTL_SECRC bit in RCTL register
- * is always set in I350, so we don't trim it.
- */
- if ((sc->sc_type != WM_T_I350) && (sc->sc_type != WM_T_I354)
- && (sc->sc_type != WM_T_I210)
- && (sc->sc_type != WM_T_I211)) {
+ */
+ if ((sc->sc_flags & WM_F_CRC_STRIP) == 0) {
if (m->m_len < ETHER_CRC_LEN) {
rxq->rxq_tail->m_len
-= (ETHER_CRC_LEN - m->m_len);
@@ -9319,7 +9335,7 @@
return;
rv = sc->phy.readreg_locked(dev, 2,
- I219_UNKNOWN1, &data);
+ I82579_UNKNOWN1, &data);
if (rv) {
sc->phy.release(sc);
return;
@@ -9330,7 +9346,7 @@
data &= ~(0x3ff << 2);
data |= (0x18 << 2);
rv = sc->phy.writereg_locked(dev,
- 2, I219_UNKNOWN1, data);
+ 2, I82579_UNKNOWN1, data);
}
sc->phy.release(sc);
if (rv)
@@ -9341,7 +9357,7 @@
return;
rv = sc->phy.writereg_locked(dev, 2,
- I219_UNKNOWN1, 0xc023);
+ I82579_UNKNOWN1, 0xc023);
sc->phy.release(sc);
if (rv)
return;
@@ -10984,7 +11000,7 @@
*
* Read a PHY register on the kumeran
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_i80003_readreg(device_t dev, int phy, int reg, uint16_t *val)
@@ -11043,7 +11059,7 @@
*
* Write a PHY register on the kumeran.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_i80003_writereg(device_t dev, int phy, int reg, uint16_t val)
@@ -11101,7 +11117,7 @@
*
* Read a PHY register on the kumeran
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_bm_readreg(device_t dev, int phy, int reg, uint16_t *val)
@@ -11148,7 +11164,7 @@
*
* Write a PHY register on the kumeran.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_bm_writereg(device_t dev, int phy, int reg, uint16_t val)
@@ -11359,7 +11375,7 @@
*
* Read a PHY register on the kumeran
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_hv_readreg(device_t dev, int phy, int reg, uint16_t *val)
@@ -11423,7 +11439,7 @@
*
* Write a PHY register on the kumeran.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_hv_writereg(device_t dev, int phy, int reg, uint16_t val)
@@ -11509,7 +11525,7 @@
*
* Read a PHY register on the 82580 and I350.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_82580_readreg(device_t dev, int phy, int reg, uint16_t *val)
@@ -11540,7 +11556,7 @@
*
* Write a PHY register on the 82580 and I350.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_82580_writereg(device_t dev, int phy, int reg, uint16_t val)
@@ -11571,7 +11587,7 @@
*
* Read a PHY register on the I2100 and I211.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_gs40g_readreg(device_t dev, int phy, int reg, uint16_t *val)
@@ -11606,7 +11622,7 @@
*
* Write a PHY register on the I210 and I211.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_gmii_gs40g_writereg(device_t dev, int phy, int reg, uint16_t val)
@@ -11893,7 +11909,7 @@
*
* Read a PHY register on the SGMII
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_sgmii_readreg(device_t dev, int phy, int reg, uint16_t *val)
@@ -11950,7 +11966,7 @@
*
* Write a PHY register on the SGMII.
* This could be handled by the PHY layer if we didn't have to lock the
- * ressource ...
+ * resource ...
*/
static int
wm_sgmii_writereg(device_t dev, int phy, int reg, uint16_t val)
@@ -15904,18 +15920,31 @@
static void
wm_copy_rx_addrs_to_phy_ich8lan(struct wm_softc *sc)
{
+
+ DPRINTF(WM_DEBUG_INIT, ("%s: %s called\n",
+ device_xname(sc->sc_dev), __func__));
+
+ if (sc->phy.acquire(sc) != 0)
+ return;
+
+ wm_copy_rx_addrs_to_phy_ich8lan_locked(sc);
+
+ sc->phy.release(sc);
+}
+
+static void
+wm_copy_rx_addrs_to_phy_ich8lan_locked(struct wm_softc *sc)
Home |
Main Index |
Thread Index |
Old Index