[src/netbsd-9]: src/sys/dev/pci Pull up following revision(s) (requested by a...

[martin <martin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/93c1bca98d4e
branches:  netbsd-9
changeset: 1002359:93c1bca98d4e
user:      martin <martin%NetBSD.org@localhost>
date:      Fri Sep 03 10:20:22 2021 +0000

description:
Pull up following revision(s) (requested by andvar in ticket #1339):

        sys/dev/pci/if_vte.c: revision 1.32

Restore original MDC speed control register value after MAC reset, if
it wasn't default. Fixes PR port-i386/53494.

ok riastradh

diffstat:

 sys/dev/pci/if_vte.c |  15 ++++++++++++---
 1 files changed, 12 insertions(+), 3 deletions(-)

diffs (45 lines):

diff -r 5cd4b996c3f8 -r 93c1bca98d4e sys/dev/pci/if_vte.c
--- a/sys/dev/pci/if_vte.c      Fri Aug 20 19:33:44 2021 +0000
+++ b/sys/dev/pci/if_vte.c      Fri Sep 03 10:20:22 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_vte.c,v 1.26.2.1 2019/11/06 09:59:39 martin Exp $   */
+/*     $NetBSD: if_vte.c,v 1.26.2.2 2021/09/03 10:20:22 martin Exp $   */
 
 /*
  * Copyright (c) 2011 Manuel Bouyer.  All rights reserved.
@@ -55,7 +55,7 @@
 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_vte.c,v 1.26.2.1 2019/11/06 09:59:39 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_vte.c,v 1.26.2.2 2021/09/03 10:20:22 martin Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -1200,9 +1200,10 @@
 static void
 vte_reset(struct vte_softc *sc)
 {
-       uint16_t mcr;
+       uint16_t mcr, mdcsc;
        int i;
 
+       mdcsc = CSR_READ_2(sc, VTE_MDCSC);
        mcr = CSR_READ_2(sc, VTE_MCR1);
        CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
        for (i = VTE_RESET_TIMEOUT; i > 0; i--) {
@@ -1220,6 +1221,14 @@
        CSR_WRITE_2(sc, VTE_MACSM, 0x0002);
        CSR_WRITE_2(sc, VTE_MACSM, 0);
        DELAY(5000);
+
+       /*
+        * On some SoCs (like Vortex86DX3) MDC speed control register value
+        * needs to be restored to original value instead of default one,
+        * otherwise some PHY registers may fail to be read.
+        */
+       if (mdcsc != MDCSC_DEFAULT)
+               CSR_WRITE_2(sc, VTE_MDCSC, mdcsc);
 }