[src/trunk]: src/sys/arch/arm Explicitly annotate FPU requirements for LLVM MC.

[joerg <joerg%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/5cad8edc9172
branches:  trunk
changeset: 1004462:5cad8edc9172
user:      joerg <joerg%NetBSD.org@localhost>
date:      Tue Oct 29 16:18:23 2019 +0000

description:
Explicitly annotate FPU requirements for LLVM MC.

When using GCC, this annotations change the global state, but there is
no push/pop functionality for .fpu to avoid this problem. The state is
local to each inline assembler block with LLVM MC.

diffstat:

 sys/arch/arm/arm32/cpuswitch.S |   8 ++++++--
 sys/arch/arm/include/armreg.h  |  24 ++++++++++++------------
 sys/arch/arm/vfp/vfp_init.c    |  12 ++++++------
 3 files changed, 24 insertions(+), 20 deletions(-)

diffs (117 lines):

diff -r 164842ecf181 -r 5cad8edc9172 sys/arch/arm/arm32/cpuswitch.S
--- a/sys/arch/arm/arm32/cpuswitch.S    Tue Oct 29 16:08:50 2019 +0000
+++ b/sys/arch/arm/arm32/cpuswitch.S    Tue Oct 29 16:18:23 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpuswitch.S,v 1.94 2019/09/13 06:30:10 skrll Exp $     */
+/*     $NetBSD: cpuswitch.S,v 1.95 2019/10/29 16:18:23 joerg Exp $     */
 
 /*
  * Copyright 2003 Wasabi Systems, Inc.
@@ -87,10 +87,14 @@
 #include <arm/asm.h>
 #include <arm/locore.h>
 
-       RCSID("$NetBSD: cpuswitch.S,v 1.94 2019/09/13 06:30:10 skrll Exp $")
+       RCSID("$NetBSD: cpuswitch.S,v 1.95 2019/10/29 16:18:23 joerg Exp $")
 
 /* LINTSTUB: include <sys/param.h> */
 
+#ifdef FPU_VFP
+       .fpu vfpv2
+#endif
+
 #undef IRQdisable
 #undef IRQenable
 
diff -r 164842ecf181 -r 5cad8edc9172 sys/arch/arm/include/armreg.h
--- a/sys/arch/arm/include/armreg.h     Tue Oct 29 16:08:50 2019 +0000
+++ b/sys/arch/arm/include/armreg.h     Tue Oct 29 16:18:23 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: armreg.h,v 1.128 2019/08/12 23:31:48 jmcneill Exp $    */
+/*     $NetBSD: armreg.h,v 1.129 2019/10/29 16:18:23 joerg Exp $       */
 
 /*
  * Copyright (c) 1998, 2001 Ben Harris
@@ -745,17 +745,17 @@
 }
 
 /* cp10 registers */
-ARMREG_READ_INLINE2(fpsid, "vmrs\t%0, fpsid") /* VFP System ID */
-ARMREG_READ_INLINE2(fpscr, "vmrs\t%0, fpscr") /* VFP Status/Control Register */
-ARMREG_WRITE_INLINE2(fpscr, "vmsr\tfpscr, %0") /* VFP Status/Control Register */
-ARMREG_READ_INLINE2(mvfr1, "vmrs\t%0, mvfr1") /* Media and VFP Feature Register 1 */
-ARMREG_READ_INLINE2(mvfr0, "vmrs\t%0, mvfr0") /* Media and VFP Feature Register 0 */
-ARMREG_READ_INLINE2(fpexc, "vmrs\t%0, fpexc") /* VFP Exception Register */
-ARMREG_WRITE_INLINE2(fpexc, "vmsr\tfpexc, %0") /* VFP Exception Register */
-ARMREG_READ_INLINE2(fpinst, "fmrx\t%0, fpinst") /* VFP Exception Instruction */
-ARMREG_WRITE_INLINE2(fpinst, "fmxr\tfpinst, %0") /* VFP Exception Instruction */
-ARMREG_READ_INLINE2(fpinst2, "fmrx\t%0, fpinst2") /* VFP Exception Instruction 2 */
-ARMREG_WRITE_INLINE2(fpinst2, "fmxr\tfpinst2, %0") /* VFP Exception Instruction 2 */
+ARMREG_READ_INLINE2(fpsid, ".fpu vfp\n vmrs\t%0, fpsid") /* VFP System ID */
+ARMREG_READ_INLINE2(fpscr, ".fpu vfp\n vmrs\t%0, fpscr") /* VFP Status/Control Register */
+ARMREG_WRITE_INLINE2(fpscr, ".fpu vfp\n vmsr\tfpscr, %0") /* VFP Status/Control Register */
+ARMREG_READ_INLINE2(mvfr1, ".fpu vfp\n vmrs\t%0, mvfr1") /* Media and VFP Feature Register 1 */
+ARMREG_READ_INLINE2(mvfr0, ".fpu vfp\n vmrs\t%0, mvfr0") /* Media and VFP Feature Register 0 */
+ARMREG_READ_INLINE2(fpexc, ".fpu vfp\n vmrs\t%0, fpexc") /* VFP Exception Register */
+ARMREG_WRITE_INLINE2(fpexc, ".fpu vfp\n vmsr\tfpexc, %0") /* VFP Exception Register */
+ARMREG_READ_INLINE2(fpinst, ".fpu vfp\n fmrx\t%0, fpinst") /* VFP Exception Instruction */
+ARMREG_WRITE_INLINE2(fpinst, ".fpu vfp\n vmsr\tfpinst, %0") /* VFP Exception Instruction */
+ARMREG_READ_INLINE2(fpinst2, ".fpu vfp\n fmrx\t%0, fpinst2") /* VFP Exception Instruction 2 */
+ARMREG_WRITE_INLINE2(fpinst2, ".fpu vfp\n fmxr\tfpinst2, %0") /* VFP Exception Instruction 2 */
 
 /* cp15 c0 registers */
 ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */
diff -r 164842ecf181 -r 5cad8edc9172 sys/arch/arm/vfp/vfp_init.c
--- a/sys/arch/arm/vfp/vfp_init.c       Tue Oct 29 16:08:50 2019 +0000
+++ b/sys/arch/arm/vfp/vfp_init.c       Tue Oct 29 16:18:23 2019 +0000
@@ -1,4 +1,4 @@
-/*      $NetBSD: vfp_init.c,v 1.63 2019/09/07 19:42:42 tnn Exp $ */
+/*      $NetBSD: vfp_init.c,v 1.64 2019/10/29 16:18:23 joerg Exp $ */
 
 /*
  * Copyright (c) 2008 ARM Ltd
@@ -32,7 +32,7 @@
 #include "opt_cputypes.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: vfp_init.c,v 1.63 2019/09/07 19:42:42 tnn Exp $");
+__KERNEL_RCSID(0, "$NetBSD: vfp_init.c,v 1.64 2019/10/29 16:18:23 joerg Exp $");
 
 #include <sys/param.h>
 #include <sys/types.h>
@@ -63,7 +63,7 @@
 load_vfpregs_lo(const uint64_t *p)
 {
        SETFPU;
-       __asm __volatile("vldmia\t%0, {d0-d15}" :: "r" (p) : "memory");
+       __asm __volatile(".fpu vfp\n vldmia\t%0, {d0-d15}" :: "r" (p) : "memory");
 }
 
 /* FSTMD <X>, {d0-d15} */
@@ -71,7 +71,7 @@
 save_vfpregs_lo(uint64_t *p)
 {
        SETFPU;
-       __asm __volatile("vstmia\t%0, {d0-d15}" :: "r" (p) : "memory");
+       __asm __volatile(".fpu vfp\n vstmia\t%0, {d0-d15}" :: "r" (p) : "memory");
 }
 
 #ifdef CPU_CORTEX
@@ -80,7 +80,7 @@
 load_vfpregs_hi(const uint64_t *p)
 {
        SETFPU;
-       __asm __volatile("vldmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory");
+       __asm __volatile(".fpu neon-vfpv4\n vldmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory");
 }
 
 /* FLDMD <X>, {d16-d31} */
@@ -88,7 +88,7 @@
 save_vfpregs_hi(uint64_t *p)
 {
        SETFPU;
-       __asm __volatile("vstmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory");
+       __asm __volatile(".fpu neon-vfpv4\nvstmia\t%0, {d16-d31}" :: "r" (&p[16]) : "memory");
 }
 #endif