[src/trunk]: src/sys/arch/arm/sunxi Add crypto engine clock

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/6baf41af0ccd
branches:  trunk
changeset: 1005438:6baf41af0ccd
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sun Dec 08 00:12:20 2019 +0000

description:
Add crypto engine clock

diffstat:

 sys/arch/arm/sunxi/sun50i_a64_ccu.c |  14 ++++++++++++--
 1 files changed, 12 insertions(+), 2 deletions(-)

diffs (49 lines):

diff -r 81ee464b5f8f -r 6baf41af0ccd sys/arch/arm/sunxi/sun50i_a64_ccu.c
--- a/sys/arch/arm/sunxi/sun50i_a64_ccu.c       Sun Dec 08 00:00:59 2019 +0000
+++ b/sys/arch/arm/sunxi/sun50i_a64_ccu.c       Sun Dec 08 00:12:20 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sun50i_a64_ccu.c,v 1.20 2019/11/24 10:27:37 jmcneill Exp $ */
+/* $NetBSD: sun50i_a64_ccu.c,v 1.21 2019/12/08 00:12:20 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -28,7 +28,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.20 2019/11/24 10:27:37 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.21 2019/12/08 00:12:20 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -60,6 +60,7 @@
 #define        SDMMC0_CLK_REG          0x088
 #define        SDMMC1_CLK_REG          0x08c
 #define        SDMMC2_CLK_REG          0x090
+#define        CE_CLK_REG              0x09c
 #define        SPI0_CLK_REG            0x0a0
 #define        SPI1_CLK_REG            0x0a4
 #define        I2SPCM0_CLK_REG         0x0b0
@@ -156,6 +157,7 @@
 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" };
 static const char *apb1_parents[] = { "ahb1" };
 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" };
+static const char *ce_parents[] = { "hosc", "pll_periph0", "pll_periph1", NULL };
 static const char *mmc_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" };
 static const char *ths_parents[] = { "hosc", NULL, NULL, NULL };
 static const char *de_parents[] = { "pll_periph0_2x", "pll_de" };
@@ -397,6 +399,14 @@
            __BIT(31),          /* enable */
            SUNXI_CCU_NM_POWER_OF_TWO|SUNXI_CCU_NM_ROUND_DOWN|SUNXI_CCU_NM_DIVIDE_BY_TWO),
 
+       SUNXI_CCU_NM(A64_CLK_CE, "ce", ce_parents,
+           CE_CLK_REG,         /* reg */
+           __BITS(17,16),      /* n */
+           __BITS(3,0),        /* m */
+           __BITS(25,24),      /* sel */
+           __BIT(31),          /* enable */
+           SUNXI_CCU_NM_POWER_OF_TWO),
+
        SUNXI_CCU_DIV_GATE(A64_CLK_THS, "ths", ths_parents,
            THS_CLK_REG,        /* reg */
            __BITS(1,0),        /* div */