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[src/trunk]: src/sys/arch/arm Really use armv7 noncache memory attribute for ...
details: https://anonhg.NetBSD.org/src/rev/464042e495a9
branches: trunk
changeset: 1008363:464042e495a9
user: skrll <skrll%NetBSD.org@localhost>
date: Fri Mar 20 19:48:03 2020 +0000
description:
Really use armv7 noncache memory attribute for early kernel mapping and
not SO
diffstat:
sys/arch/arm/arm/armv6_start.S | 10 +++++-----
sys/arch/arm/arm32/genassym.cf | 3 ++-
2 files changed, 7 insertions(+), 6 deletions(-)
diffs (48 lines):
diff -r e89c254fcbbd -r 464042e495a9 sys/arch/arm/arm/armv6_start.S
--- a/sys/arch/arm/arm/armv6_start.S Fri Mar 20 19:08:54 2020 +0000
+++ b/sys/arch/arm/arm/armv6_start.S Fri Mar 20 19:48:03 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armv6_start.S,v 1.15 2020/02/15 08:16:10 skrll Exp $ */
+/* $NetBSD: armv6_start.S,v 1.16 2020/03/20 19:48:03 skrll Exp $ */
/*-
* Copyright (c) 2012, 2017, 2018 The NetBSD Foundation, Inc.
@@ -257,8 +257,8 @@
ldr r0, =(L1_S_SIZE - 1)
bic R_PA, R_PA, r0
- // attribute to map kernel - run without L1_S_CACHEABLE
- ldr R_ATTR, =(L1_S_PROTO | L1_S_AP_KRW)
+ // attribute to map kernel
+ ldr R_ATTR, =(L1_S_PROTO | L1_S_AP_KRW | L1_S_NOCACHE)
bl arm_boot_l1pt_init
/*
@@ -287,8 +287,8 @@
adr R_PA, generic_start // PA of kernel
bic R_PA, r2 // ...rounded down to L1_S boundary
- // attribute to map kernel - run without L1_S_CACHEABLE
- ldr R_ATTR, =(L1_S_PROTO | L1_S_AP_KRW)
+ // attribute to map kernel
+ ldr R_ATTR, =(L1_S_PROTO | L1_S_AP_KRW | L1_S_NOCACHE)
bl arm_boot_l1pt_entry
#if defined(FDTBASE)
diff -r e89c254fcbbd -r 464042e495a9 sys/arch/arm/arm32/genassym.cf
--- a/sys/arch/arm/arm32/genassym.cf Fri Mar 20 19:08:54 2020 +0000
+++ b/sys/arch/arm/arm32/genassym.cf Fri Mar 20 19:48:03 2020 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.88 2020/02/18 10:33:38 skrll Exp $
+# $NetBSD: genassym.cf,v 1.89 2020/03/20 19:48:03 skrll Exp $
# Copyright (c) 1982, 1990 The Regents of the University of California.
# All rights reserved.
@@ -109,6 +109,7 @@
define L1_S_SHIFT L1_S_SHIFT
define L1_S_SIZE L1_S_SIZE
define L1_S_CACHEABLE L1_S_C|L1_S_B|L1_S_V6_S
+define L1_S_NOCACHE L1_S_XS_TEX(1)
define L1_S_B L1_S_B
define L1_S_C L1_S_C
define L1_S_V6_S L1_S_V6_S
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