[src/trunk]: src/sys/arch/arm/sunxi Add A20 CLK_OUT_A and CLK_OUT_B clocks

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/68379e56f437
branches:  trunk
changeset: 1009905:68379e56f437
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Thu May 07 11:24:47 2020 +0000

description:
Add A20 CLK_OUT_A and CLK_OUT_B clocks

diffstat:

 sys/arch/arm/sunxi/sun4i_a10_ccu.c |  24 ++++++++++++++++++++++--
 1 files changed, 22 insertions(+), 2 deletions(-)

diffs (59 lines):

diff -r 37377ff0b0d9 -r 68379e56f437 sys/arch/arm/sunxi/sun4i_a10_ccu.c
--- a/sys/arch/arm/sunxi/sun4i_a10_ccu.c        Thu May 07 09:13:06 2020 +0000
+++ b/sys/arch/arm/sunxi/sun4i_a10_ccu.c        Thu May 07 11:24:47 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sun4i_a10_ccu.c,v 1.11 2019/08/01 22:23:16 tnn Exp $ */
+/* $NetBSD: sun4i_a10_ccu.c,v 1.12 2020/05/07 11:24:47 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -28,7 +28,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.11 2019/08/01 22:23:16 tnn Exp $");
+__KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.12 2020/05/07 11:24:47 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -82,6 +82,8 @@
 #define        HDMI_CLOCK_CFG_REG      0x150
 #define        MALI_CLOCK_CFG_REG      0x154
 #define        IEP_SCLK_CFG_REG        0x160
+#define        CLK_OUTA_REG            0x1f0
+#define        CLK_OUTB_REG            0x1f4
 
 static int sun4i_a10_ccu_match(device_t, cfdata_t, void *);
 static void sun4i_a10_ccu_attach(device_t, device_t, void *);
@@ -123,6 +125,7 @@
 static const char *sata_parents[] = { "pll6_periph_sata", "external" };
 static const char *de_parents[] = { "pll_video0", "pll_video1", "pll_ddr_other" };
 static const char *lcd_parents[] = { "pll_video0", "pll_video1", "pll_video0x2", "pll_video1x2" };
+static const char *out_parents[] = { "losc" /* really OSC24MHz/750 */, "losc", "osc24m" };
 
 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_pll1_table[] = {
        { 1008000000, 21, 1, 0, 0 },
@@ -484,6 +487,23 @@
            0                           /* flags */
            ),
 
+       /* A20 specific */
+       SUNXI_CCU_NM(A20_CLK_OUT_A, "outa", out_parents,
+           CLK_OUTA_REG,               /* reg */
+           __BITS(21,20),              /* n */
+           __BITS(12,8),               /* m */
+           __BITS(25,24),              /* sel */
+           __BIT(31),                  /* enable */
+           SUNXI_CCU_NM_POWER_OF_TWO),
+
+       SUNXI_CCU_NM(A20_CLK_OUT_B, "outb", out_parents,
+           CLK_OUTB_REG,               /* reg */
+           __BITS(21,20),              /* n */
+           __BITS(12,8),               /* m */
+           __BITS(25,24),              /* sel */
+           __BIT(31),                  /* enable */
+           SUNXI_CCU_NM_POWER_OF_TWO),
+
        /* AHB_GATING_REG0 */
        SUNXI_CCU_GATE(A10_CLK_AHB_OTG, "ahb-otg", "ahb",
            AHB_GATING_REG0, 0),