[src/trunk]: src/sys/arch/aarch64 "options ARMV83_PAC" is now supported for g...

[ryo <ryo%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/e5ecc120921e
branches:  trunk
changeset: 1009996:e5ecc120921e
user:      ryo <ryo%NetBSD.org@localhost>
date:      Mon May 11 03:00:57 2020 +0000

description:
"options ARMV83_PAC" is now supported for gcc as well.

- add "-msign-return-address=all" to CFLAGS for gcc when specified options ARMV83_PAC
- AARCH64REG_{READ,WRITE}_INLINE3 macro can now use the APIAKey registers in both gcc and llvm.
  llvm requires asm(".arch armv8.3-a"), whereas gcc requires __attribute__((target("arch=armv8.3-a"))).
- use ".arch armv8.3-a" rather than ".arch armv8.3-a+pac" in *.S for llvm.

diffstat:

 sys/arch/aarch64/conf/Makefile.aarch64 |  11 ++++++-
 sys/arch/aarch64/include/armreg.h      |  51 +++++++++++++++++++--------------
 sys/arch/aarch64/include/asm.h         |   4 +-
 3 files changed, 41 insertions(+), 25 deletions(-)

diffs (140 lines):

diff -r edc052361336 -r e5ecc120921e sys/arch/aarch64/conf/Makefile.aarch64
--- a/sys/arch/aarch64/conf/Makefile.aarch64    Sun May 10 22:38:51 2020 +0000
+++ b/sys/arch/aarch64/conf/Makefile.aarch64    Mon May 11 03:00:57 2020 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: Makefile.aarch64,v 1.20 2020/04/13 07:32:36 maxv Exp $
+#      $NetBSD: Makefile.aarch64,v 1.21 2020/05/11 03:00:57 ryo Exp $
 
 # Makefile for NetBSD
 #
@@ -52,6 +52,15 @@
 .endif
 .endif
 
+.if ${HAVE_GCC:U0} > 0
+.if ${ARMV83_PAC:U0} > 0
+CFLAGS+=       -msign-return-address=all
+.endif
+.if ${ARMV85_BTI:U0} > 0
+# XXX: notyet for gcc
+.endif
+.endif
+
 .if ${KASAN:U0} > 0 && ${HAVE_GCC:U0} > 0
 KASANFLAGS=    -fsanitize=kernel-address \
                --param asan-globals=1 --param asan-stack=1 \
diff -r edc052361336 -r e5ecc120921e sys/arch/aarch64/include/armreg.h
--- a/sys/arch/aarch64/include/armreg.h Sun May 10 22:38:51 2020 +0000
+++ b/sys/arch/aarch64/include/armreg.h Mon May 11 03:00:57 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.41 2020/05/10 21:40:38 riastradh Exp $ */
+/* $NetBSD: armreg.h,v 1.42 2020/05/11 03:00:57 ryo Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -35,23 +35,39 @@
 #include <arm/cputypes.h>
 #include <sys/types.h>
 
-#define AARCH64REG_READ_INLINE3(regname, regdesc, fnattrs)     \
-static __inline uint64_t fnattrs                               \
+#ifdef __clang__
+#define ATTR_ARCH(arch)                        ".arch " arch ";"
+#define ATTR_TARGET_ARCH(x)
+#define ASM_ARCH(x)                    x
+#else
+#define ATTR_ARCH(arch)                        __attribute__((target("arch=" arch)))
+#define ATTR_TARGET_ARCH(x)            x
+#define ASM_ARCH(x)
+#endif
+
+#define AARCH64REG_READ_INLINE3(regname, regdesc, arch)                \
+static __inline uint64_t ATTR_TARGET_ARCH(arch)                        \
 reg_##regname##_read(void)                                     \
 {                                                              \
        uint64_t __rv;                                          \
-       __asm __volatile("mrs %0, " #regdesc : "=r"(__rv));     \
+       __asm __volatile(                                       \
+           ASM_ARCH(arch)                                      \
+           "mrs %0, " #regdesc : "=r"(__rv)                    \
+       );                                                      \
        return __rv;                                            \
 }
 
 #define AARCH64REG_READ_INLINE2(regname, regdesc)              \
        AARCH64REG_READ_INLINE3(regname, regdesc, )
 
-#define AARCH64REG_WRITE_INLINE3(regname, regdesc, fnattrs)    \
-static __inline void fnattrs                                   \
+#define AARCH64REG_WRITE_INLINE3(regname, regdesc, arch)       \
+static __inline void ATTR_TARGET_ARCH(arch)                    \
 reg_##regname##_write(uint64_t __val)                          \
 {                                                              \
-       __asm __volatile("msr " #regdesc ", %0" :: "r"(__val)); \
+       __asm __volatile(                                       \
+           ASM_ARCH(arch)                                      \
+           "msr " #regdesc ", %0" :: "r"(__val)                \
+       );                                                      \
 }
 
 #define AARCH64REG_WRITE_INLINE2(regname, regdesc)             \
@@ -380,7 +396,7 @@
 #define         ID_AA64MMFR1_EL1_HAFDBS_AD      2
 
 AARCH64REG_READ_INLINE3(id_aa64mmfr2_el1, id_aa64mmfr2_el1,
-    __attribute__((target("arch=armv8.2-a"))))
+    ATTR_ARCH("armv8.2-a"))
 
 #define        ID_AA64MMFR2_EL1_E0PD           __BITS(63,60)
 #define         ID_AA64MMFR2_EL1_E0PD_NONE      0
@@ -548,6 +564,11 @@
 /*
  * These are read/write registers
  */
+AARCH64REG_READ_INLINE3(APIAKeyLo_EL1, apiakeylo_el1, ATTR_ARCH("armv8.3-a"))
+AARCH64REG_WRITE_INLINE3(APIAKeyLo_EL1, apiakeylo_el1, ATTR_ARCH("armv8.3-a"))
+AARCH64REG_READ_INLINE3(APIAKeyHi_EL1, apiakeyhi_el1, ATTR_ARCH("armv8.3-a"))
+AARCH64REG_WRITE_INLINE3(APIAKeyHi_EL1, apiakeyhi_el1, ATTR_ARCH("armv8.3-a"))
+
 AARCH64REG_READ_INLINE(cpacr_el1)      // Coprocessor Access Control Regiser
 AARCH64REG_WRITE_INLINE(cpacr_el1)
 
@@ -786,20 +807,6 @@
 #define        SCTLR_ATA               __BIT(43)
 #define        SCTLR_DSSBS             __BIT(44)
 
-static __inline void
-reg_APIAKeyLo_EL1_write(uint64_t __val)
-{
-       __asm __volatile(".arch armv8.3-a+pac\n"
-           "msr APIAKeyLo_EL1, %0" :: "r"(__val));
-}
-
-static __inline void
-reg_APIAKeyHi_EL1_write(uint64_t __val)
-{
-       __asm __volatile(".arch armv8.3-a+pac\n"
-           "msr APIAKeyHi_EL1, %0" :: "r"(__val));
-}
-
 #define        PTR_VA_RANGE_SELECT     __BIT(55)
 #define        PTR_PAC_MASK            (__BITS(63,56) | __BITS(54, 48))
 
diff -r edc052361336 -r e5ecc120921e sys/arch/aarch64/include/asm.h
--- a/sys/arch/aarch64/include/asm.h    Sun May 10 22:38:51 2020 +0000
+++ b/sys/arch/aarch64/include/asm.h    Mon May 11 03:00:57 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: asm.h,v 1.7 2020/04/12 07:49:58 maxv Exp $ */
+/* $NetBSD: asm.h,v 1.8 2020/05/11 03:00:57 ryo Exp $ */
 
 #ifndef _AARCH64_ASM_H_
 #define _AARCH64_ASM_H_
@@ -38,7 +38,7 @@
  */
 #ifdef ARMV83_PAC
 #define ARMV8_DEFINE_OPTIONS   \
-       .arch armv8.3-a+pac
+       .arch armv8.3-a
 #else
 #define ARMV8_DEFINE_OPTIONS   /* nothing */
 #endif