[src/trunk]: src/sys/arch/mips/mips CN70XX has a config4 CP0 register.

[simonb <simonb%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/0c9950f1efca
branches:  trunk
changeset: 1012428:0c9950f1efca
user:      simonb <simonb%NetBSD.org@localhost>
date:      Fri Jul 31 02:58:03 2020 +0000

description:
CN70XX has a config4 CP0 register.

diffstat:

 sys/arch/mips/mips/mips_machdep.c |  7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diffs (28 lines):

diff -r 050895d1a527 -r 0c9950f1efca sys/arch/mips/mips/mips_machdep.c
--- a/sys/arch/mips/mips/mips_machdep.c Fri Jul 31 02:56:48 2020 +0000
+++ b/sys/arch/mips/mips/mips_machdep.c Fri Jul 31 02:58:03 2020 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mips_machdep.c,v 1.295 2020/07/13 05:20:45 simonb Exp $        */
+/*     $NetBSD: mips_machdep.c,v 1.296 2020/07/31 02:58:03 simonb Exp $        */
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -111,7 +111,7 @@
  */
 
 #include <sys/cdefs.h>                 /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.295 2020/07/13 05:20:45 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.296 2020/07/31 02:58:03 simonb Exp $");
 
 #define __INTR_PRIVATE
 #include "opt_cputype.h"
@@ -674,7 +674,8 @@
          MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR,
          MIPS_CP0FL_USE |
          MIPS_CP0FL_EBASE | MIPS_CP0FL_CONFIG |
-         MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | MIPS_CP0FL_CONFIG3,
+         MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | MIPS_CP0FL_CONFIG3 |
+         MIPS_CP0FL_CONFIG4,
          0,
          "CN70xx/CN71xx"       },