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[src/trunk]: src/sys/arch Add support for Allwinner V3s, from Rui-Xiang Guo.
details: https://anonhg.NetBSD.org/src/rev/7bbb70ca3f60
branches: trunk
changeset: 1021062:7bbb70ca3f60
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Wed May 05 10:24:04 2021 +0000
description:
Add support for Allwinner V3s, from Rui-Xiang Guo.
diffstat:
sys/arch/arm/sunxi/files.sunxi | 13 +-
sys/arch/arm/sunxi/sun6i_dma.c | 16 +-
sys/arch/arm/sunxi/sun8i_v3s_ccu.c | 417 ++++++++++++++++++++++++++++++++
sys/arch/arm/sunxi/sun8i_v3s_ccu.h | 133 ++++++++++
sys/arch/arm/sunxi/sun8i_v3s_codec.c | 447 +++++++++++++++++++++++++++++++++++
sys/arch/arm/sunxi/sunxi_codec.c | 5 +-
sys/arch/arm/sunxi/sunxi_codec.h | 12 +-
sys/arch/evbarm/conf/GENERIC | 4 +-
8 files changed, 1040 insertions(+), 7 deletions(-)
diffs (truncated from 1179 to 300 lines):
diff -r 3b14423600c8 -r 7bbb70ca3f60 sys/arch/arm/sunxi/files.sunxi
--- a/sys/arch/arm/sunxi/files.sunxi Wed May 05 07:41:48 2021 +0000
+++ b/sys/arch/arm/sunxi/files.sunxi Wed May 05 10:24:04 2021 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.sunxi,v 1.68 2020/03/24 22:09:50 tnn Exp $
+# $NetBSD: files.sunxi,v 1.69 2021/05/05 10:24:04 jmcneill Exp $
#
# Configuration info for Allwinner sunxi family SoCs
#
@@ -52,6 +52,11 @@
attach sun8ih3rccu at fdt with sunxi_h3_r_ccu
file arch/arm/sunxi/sun8i_h3_r_ccu.c sunxi_h3_r_ccu
+# CCU (V3s)
+device sun8iv3sccu: sunxi_ccu
+attach sun8iv3sccu at fdt with sunxi_v3s_ccu
+file arch/arm/sunxi/sun8i_v3s_ccu.c sunxi_v3s_ccu
+
# CCU (A80)
device sun9ia80ccu: sunxi_ccu
attach sun9ia80ccu at fdt with sunxi_a80_ccu
@@ -233,6 +238,11 @@
attach h3codec at fdt with h3_codec
file arch/arm/sunxi/sun8i_h3_codec.c h3_codec needs-flag
+# V3s Audio codec (analog part)
+device v3scodec
+attach v3scodec at fdt with v3s_codec
+file arch/arm/sunxi/sun8i_v3s_codec.c v3s_codec needs-flag
+
# A64 Audio codec (analog part)
device a64acodec
attach a64acodec at fdt with a64_acodec
@@ -375,6 +385,7 @@
defflag opt_soc.h SOC_SUN8I: SOC_SUNXI
defflag opt_soc.h SOC_SUN8I_A83T: SOC_SUN8I, SOC_SUNXI_MC
defflag opt_soc.h SOC_SUN8I_H3: SOC_SUN8I
+defflag opt_soc.h SOC_SUN8I_V3S: SOC_SUN8I
defflag opt_soc.h SOC_SUN9I: SOC_SUNXI
defflag opt_soc.h SOC_SUN9I_A80: SOC_SUN9I, SOC_SUNXI_MC
defflag opt_soc.h SOC_SUN50I: SOC_SUNXI
diff -r 3b14423600c8 -r 7bbb70ca3f60 sys/arch/arm/sunxi/sun6i_dma.c
--- a/sys/arch/arm/sunxi/sun6i_dma.c Wed May 05 07:41:48 2021 +0000
+++ b/sys/arch/arm/sunxi/sun6i_dma.c Wed May 05 10:24:04 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sun6i_dma.c,v 1.14 2021/01/27 03:10:20 thorpej Exp $ */
+/* $NetBSD: sun6i_dma.c,v 1.15 2021/05/05 10:24:04 jmcneill Exp $ */
/*-
* Copyright (c) 2014-2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
#include "opt_ddb.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sun6i_dma.c,v 1.14 2021/01/27 03:10:20 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sun6i_dma.c,v 1.15 2021/05/05 10:24:04 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -141,6 +141,16 @@
.widths = WIDTHS_1_2_4_8,
};
+static const struct sun6idma_config sun8i_v3s_dma_config = {
+ .num_channels = 8,
+ .autogate = true,
+ .autogate_reg = 0x20,
+ .autogate_mask = 0x4,
+ .burst_mask = __BITS(8,7),
+ .bursts = BURSTS_1_8,
+ .widths = WIDTHS_1_2_4,
+};
+
static const struct sun6idma_config sun50i_a64_dma_config = {
.num_channels = 8,
.autogate = true,
@@ -158,6 +168,8 @@
.data = &sun8i_a83t_dma_config },
{ .compat = "allwinner,sun8i-h3-dma",
.data = &sun8i_h3_dma_config },
+ { .compat = "allwinner,sun8i-v3s-dma",
+ .data = &sun8i_v3s_dma_config },
{ .compat = "allwinner,sun50i-a64-dma",
.data = &sun50i_a64_dma_config },
diff -r 3b14423600c8 -r 7bbb70ca3f60 sys/arch/arm/sunxi/sun8i_v3s_ccu.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/sunxi/sun8i_v3s_ccu.c Wed May 05 10:24:04 2021 +0000
@@ -0,0 +1,417 @@
+/* $NetBSD: sun8i_v3s_ccu.c,v 1.1 2021/05/05 10:24:04 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2021 Rui-Xiang Guo
+ * Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * Copyright (c) 2017 Emmanuel Vadot <manu%freebsd.org@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: sun8i_v3s_ccu.c,v 1.1 2021/05/05 10:24:04 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/sunxi/sunxi_ccu.h>
+#include <arm/sunxi/sun8i_v3s_ccu.h>
+
+#define PLL_CPU_CTRL_REG 0x000
+#define PLL_AUDIO_CTRL_REG 0x008
+#define PLL_VIDEO_CTRL_REG 0x010
+#define PLL_PERIPH0_CTRL_REG 0x028
+#define AHB1_APB1_CFG_REG 0x054
+#define APB2_CFG_REG 0x058
+#define AHB2_CFG_REG 0x05c
+#define AHB2_CLK_CFG __BITS(1,0)
+#define AHB2_CLK_CFG_PLL_PERIPH0_2 1
+#define BUS_CLK_GATING_REG0 0x060
+#define BUS_CLK_GATING_REG1 0x064
+#define BUS_CLK_GATING_REG2 0x068
+#define BUS_CLK_GATING_REG3 0x06c
+#define BUS_CLK_GATING_REG4 0x070
+#define SDMMC0_CLK_REG 0x088
+#define SDMMC1_CLK_REG 0x08c
+#define SDMMC2_CLK_REG 0x090
+#define SPI_CLK_REG 0x0a0
+#define USBPHY_CFG_REG 0x0cc
+#define MBUS_RST_REG 0x0fc
+#define DE_CLK_REG 0x104
+#define TCON_CLK_REG 0x118
+#define AC_DIG_CLK_REG 0x140
+#define BUS_SOFT_RST_REG0 0x2c0
+#define BUS_SOFT_RST_REG1 0x2c4
+#define BUS_SOFT_RST_REG2 0x2c8
+#define BUS_SOFT_RST_REG3 0x2d0
+#define BUS_SOFT_RST_REG4 0x2d8
+
+static int sun8i_v3s_ccu_match(device_t, cfdata_t, void *);
+static void sun8i_v3s_ccu_attach(device_t, device_t, void *);
+
+static const struct device_compatible_entry compat_data[] = {
+ { .compat = "allwinner,sun8i-v3s-ccu" },
+ DEVICE_COMPAT_EOL
+};
+
+CFATTACH_DECL_NEW(sunxi_v3s_ccu, sizeof(struct sunxi_ccu_softc),
+ sun8i_v3s_ccu_match, sun8i_v3s_ccu_attach, NULL, NULL);
+
+static struct sunxi_ccu_reset sun8i_v3s_ccu_resets[] = {
+ SUNXI_CCU_RESET(V3S_RST_USBPHY, USBPHY_CFG_REG, 0),
+
+ SUNXI_CCU_RESET(V3S_RST_MBUS, MBUS_RST_REG, 31),
+
+ SUNXI_CCU_RESET(V3S_RST_BUS_CE, BUS_SOFT_RST_REG0, 5),
+ SUNXI_CCU_RESET(V3S_RST_BUS_DMA, BUS_SOFT_RST_REG0, 6),
+ SUNXI_CCU_RESET(V3S_RST_BUS_MMC0, BUS_SOFT_RST_REG0, 8),
+ SUNXI_CCU_RESET(V3S_RST_BUS_MMC1, BUS_SOFT_RST_REG0, 9),
+ SUNXI_CCU_RESET(V3S_RST_BUS_MMC2, BUS_SOFT_RST_REG0, 10),
+ SUNXI_CCU_RESET(V3S_RST_BUS_DRAM, BUS_SOFT_RST_REG0, 14),
+ SUNXI_CCU_RESET(V3S_RST_BUS_EMAC, BUS_SOFT_RST_REG0, 17),
+ SUNXI_CCU_RESET(V3S_RST_BUS_HSTIMER, BUS_SOFT_RST_REG0, 19),
+ SUNXI_CCU_RESET(V3S_RST_BUS_SPI, BUS_SOFT_RST_REG0, 20),
+ SUNXI_CCU_RESET(V3S_RST_BUS_OTG, BUS_SOFT_RST_REG0, 24),
+ SUNXI_CCU_RESET(V3S_RST_BUS_EHCI, BUS_SOFT_RST_REG0, 26),
+ SUNXI_CCU_RESET(V3S_RST_BUS_OHCI, BUS_SOFT_RST_REG0, 29),
+
+ SUNXI_CCU_RESET(V3S_RST_BUS_VE, BUS_SOFT_RST_REG1, 0),
+ SUNXI_CCU_RESET(V3S_RST_BUS_TCON, BUS_SOFT_RST_REG1, 4),
+ SUNXI_CCU_RESET(V3S_RST_BUS_CSI, BUS_SOFT_RST_REG1, 8),
+ SUNXI_CCU_RESET(V3S_RST_BUS_DE, BUS_SOFT_RST_REG1, 12),
+ SUNXI_CCU_RESET(V3S_RST_BUS_DBG, BUS_SOFT_RST_REG1, 31),
+
+ SUNXI_CCU_RESET(V3S_RST_BUS_EPHY, BUS_SOFT_RST_REG2, 2),
+
+ SUNXI_CCU_RESET(V3S_RST_BUS_CODEC, BUS_SOFT_RST_REG3, 0),
+
+ SUNXI_CCU_RESET(V3S_RST_BUS_I2C0, BUS_SOFT_RST_REG4, 0),
+ SUNXI_CCU_RESET(V3S_RST_BUS_I2C1, BUS_SOFT_RST_REG4, 1),
+ SUNXI_CCU_RESET(V3S_RST_BUS_UART0, BUS_SOFT_RST_REG4, 16),
+ SUNXI_CCU_RESET(V3S_RST_BUS_UART1, BUS_SOFT_RST_REG4, 17),
+ SUNXI_CCU_RESET(V3S_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18),
+};
+
+static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" };
+static const char *ahb2_parents[] = { "ahb1", "pll_periph0" };
+static const char *apb1_parents[] = { "ahb1" };
+static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" };
+static const char *mod_parents[] = { "hosc", "pll_periph0", "pll_periph1" };
+static const char *tcon_parents[] = { "pll_video" };
+
+static const struct sunxi_ccu_nkmp_tbl sun8i_v3s_cpu_table[] = {
+ { 60000000, 9, 0, 0, 2 },
+ { 66000000, 10, 0, 0, 2 },
+ { 72000000, 11, 0, 0, 2 },
+ { 78000000, 12, 0, 0, 2 },
+ { 84000000, 13, 0, 0, 2 },
+ { 90000000, 14, 0, 0, 2 },
+ { 96000000, 15, 0, 0, 2 },
+ { 102000000, 16, 0, 0, 2 },
+ { 108000000, 17, 0, 0, 2 },
+ { 114000000, 18, 0, 0, 2 },
+ { 120000000, 9, 0, 0, 1 },
+ { 132000000, 10, 0, 0, 1 },
+ { 144000000, 11, 0, 0, 1 },
+ { 156000000, 12, 0, 0, 1 },
+ { 168000000, 13, 0, 0, 1 },
+ { 180000000, 14, 0, 0, 1 },
+ { 192000000, 15, 0, 0, 1 },
+ { 204000000, 16, 0, 0, 1 },
+ { 216000000, 17, 0, 0, 1 },
+ { 228000000, 18, 0, 0, 1 },
+ { 240000000, 9, 0, 0, 0 },
+ { 264000000, 10, 0, 0, 0 },
+ { 288000000, 11, 0, 0, 0 },
+ { 312000000, 12, 0, 0, 0 },
+ { 336000000, 13, 0, 0, 0 },
+ { 360000000, 14, 0, 0, 0 },
+ { 384000000, 15, 0, 0, 0 },
+ { 408000000, 16, 0, 0, 0 },
+ { 432000000, 17, 0, 0, 0 },
+ { 456000000, 18, 0, 0, 0 },
+ { 480000000, 19, 0, 0, 0 },
+ { 504000000, 20, 0, 0, 0 },
+ { 528000000, 21, 0, 0, 0 },
+ { 552000000, 22, 0, 0, 0 },
+ { 576000000, 23, 0, 0, 0 },
+ { 600000000, 24, 0, 0, 0 },
+ { 624000000, 25, 0, 0, 0 },
+ { 648000000, 26, 0, 0, 0 },
+ { 672000000, 27, 0, 0, 0 },
+ { 696000000, 28, 0, 0, 0 },
+ { 720000000, 29, 0, 0, 0 },
+ { 768000000, 15, 1, 0, 0 },
+ { 792000000, 10, 2, 0, 0 },
+ { 816000000, 16, 1, 0, 0 },
+ { 864000000, 17, 1, 0, 0 },
+ { 912000000, 18, 1, 0, 0 },
+ { 936000000, 12, 2, 0, 0 },
+ { 960000000, 19, 1, 0, 0 },
+ { 1008000000, 20, 1, 0, 0 },
+ { 1056000000, 21, 1, 0, 0 },
+ { 1080000000, 14, 2, 0, 0 },
+ { 1104000000, 22, 1, 0, 0 },
+ { 1152000000, 23, 1, 0, 0 },
+ { 1200000000, 24, 1, 0, 0 },
+ { 1224000000, 16, 2, 0, 0 },
+ { 1248000000, 25, 1, 0, 0 },
+ { 1296000000, 26, 1, 0, 0 },
+ { 1344000000, 27, 1, 0, 0 },
+ { 1368000000, 18, 2, 0, 0 },
+ { 1392000000, 28, 1, 0, 0 },
+ { 1440000000, 29, 1, 0, 0 },
+ { 1512000000, 20, 2, 0, 0 },
+ { 1536000000, 15, 3, 0, 0 },
+ { 1584000000, 21, 2, 0, 0 },
+ { 1632000000, 16, 3, 0, 0 },
+ { 1656000000, 22, 2, 0, 0 },
+ { 1728000000, 23, 2, 0, 0 },
+ { 1800000000, 24, 2, 0, 0 },
+ { 1824000000, 18, 3, 0, 0 },
+ { 1872000000, 25, 2, 0, 0 },
+ { 0 }
+};
+
+static const struct sunxi_ccu_nkmp_tbl sun8i_v3s_ac_dig_table[] = {
+ { 24576000, 13, 0, 0, 13 },
+ { 0 }
+};
+
+static struct sunxi_ccu_clk sun8i_v3s_ccu_clks[] = {
+ SUNXI_CCU_NKMP_TABLE(V3S_CLK_CPU, "pll_cpu", "hosc",
+ PLL_CPU_CTRL_REG, /* reg */
+ __BITS(12,8), /* n */
+ __BITS(5,4), /* k */
+ __BITS(1,0), /* m */
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