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[src/trunk]: src/sys/arch arm: rockchip: Add support for RK3288 SoC.
details: https://anonhg.NetBSD.org/src/rev/9dd7fe02b248
branches: trunk
changeset: 1025560:9dd7fe02b248
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Fri Nov 12 22:02:08 2021 +0000
description:
arm: rockchip: Add support for RK3288 SoC.
The Rockchip RK3288 is a quad core Cortex-A17 SoC.
diffstat:
sys/arch/arm/rockchip/files.rockchip | 31 ++-
sys/arch/arm/rockchip/rk3066_smp.c | 166 ++++++++++++++
sys/arch/arm/rockchip/rk3288_cru.c | 309 ++++++++++++++++++++++++++
sys/arch/arm/rockchip/rk3288_cru.h | 209 +++++++++++++++++
sys/arch/arm/rockchip/rk3288_iomux.c | 367 +++++++++++++++++++++++++++++++
sys/arch/arm/rockchip/rk3288_platform.h | 40 +++
sys/arch/arm/rockchip/rk3288_usb.c | 183 +++++++++++++++
sys/arch/arm/rockchip/rk3328_cru.c | 5 +-
sys/arch/arm/rockchip/rk3399_cru.c | 5 +-
sys/arch/arm/rockchip/rk_cru.h | 27 ++-
sys/arch/arm/rockchip/rk_cru_composite.c | 17 +-
sys/arch/arm/rockchip/rk_cru_pll.c | 64 +++-
sys/arch/arm/rockchip/rk_gmac.c | 111 +++++++++-
sys/arch/arm/rockchip/rk_i2c.c | 25 +-
sys/arch/arm/rockchip/rk_platform.c | 95 +++++++-
sys/arch/evbarm/conf/GENERIC | 11 +-
sys/arch/evbarm/conf/files.generic | 3 +-
17 files changed, 1625 insertions(+), 43 deletions(-)
diffs (truncated from 2075 to 300 lines):
diff -r 03f45eccd1cc -r 9dd7fe02b248 sys/arch/arm/rockchip/files.rockchip
--- a/sys/arch/arm/rockchip/files.rockchip Fri Nov 12 21:59:04 2021 +0000
+++ b/sys/arch/arm/rockchip/files.rockchip Fri Nov 12 22:02:08 2021 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.rockchip,v 1.24 2020/05/17 19:57:25 riastradh Exp $
+# $NetBSD: files.rockchip,v 1.25 2021/11/12 22:02:08 jmcneill Exp $
#
# Configuration info for Rockchip family SoCs
#
@@ -6,6 +6,8 @@
file arch/arm/rockchip/rk_platform.c soc_rockchip
+file arch/arm/rockchip/rk3066_smp.c soc_rk3288
+
# Clock and reset unit (CRU)
device rkcru: rk_cru
file arch/arm/rockchip/rk_cru.c rk_cru
@@ -15,6 +17,14 @@
file arch/arm/rockchip/rk_cru_mux.c rk_cru
file arch/arm/rockchip/rk_cru_pll.c rk_cru
+ifdef arm
+
+# RK3288 clock and reset unit
+attach rkcru at fdt with rk3288_cru
+file arch/arm/rockchip/rk3288_cru.c rk3288_cru & soc_rk3288
+
+else
+
# RK3328 clock and reset unit
attach rkcru at fdt with rk3328_cru
file arch/arm/rockchip/rk3328_cru.c rk3328_cru & soc_rk3328
@@ -25,13 +35,25 @@
attach rkcru at fdt with rk3399_pmucru
file arch/arm/rockchip/rk3399_pmucru.c rk3399_pmucru & soc_rk3399
+endif
+
# IOMUX control
device rkiomux { }
+
+ifdef arm
+
+attach rkiomux at fdt with rk3288_iomux
+file arch/arm/rockchip/rk3288_iomux.c rk3288_iomux & soc_rk3288
+
+else
+
attach rkiomux at fdt with rk3328_iomux
file arch/arm/rockchip/rk3328_iomux.c rk3328_iomux & soc_rk3328
attach rkiomux at fdt with rk3399_iomux
file arch/arm/rockchip/rk3399_iomux.c rk3399_iomux & soc_rk3399
+endif
+
# GPIO
device rkgpio: gpiobus
attach rkgpio at rkiomux with rk_gpio
@@ -54,6 +76,12 @@
attach rkusbphy at rkusb with rk_usbphy
file arch/arm/rockchip/rk_usb.c rk_usb | rk_usbphy
+device rk3288usb { }
+attach rk3288usb at fdt with rk3288_usb
+device rk3288usbphy
+attach rk3288usbphy at rk3288usb with rk3288_usbphy
+file arch/arm/rockchip/rk3288_usb.c rk3288_usb | rk3288_usbphy
+
# GMAC
attach awge at fdt with rk_gmac
file arch/arm/rockchip/rk_gmac.c rk_gmac
@@ -119,5 +147,6 @@
# SOC parameters
defflag opt_soc.h SOC_ROCKCHIP
+defflag opt_soc.h SOC_RK3288: SOC_ROCKCHIP
defflag opt_soc.h SOC_RK3328: SOC_ROCKCHIP
defflag opt_soc.h SOC_RK3399: SOC_ROCKCHIP
diff -r 03f45eccd1cc -r 9dd7fe02b248 sys/arch/arm/rockchip/rk3066_smp.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/rockchip/rk3066_smp.c Fri Nov 12 22:02:08 2021 +0000
@@ -0,0 +1,166 @@
+/* $NetBSD: rk3066_smp.c,v 1.1 2021/11/12 22:02:08 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2021 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_soc.h"
+#include "opt_multiprocessor.h"
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: rk3066_smp.c,v 1.1 2021/11/12 22:02:08 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+
+#include <dev/fdt/fdtvar.h>
+#include <arm/fdt/arm_fdtvar.h>
+
+#include <uvm/uvm_extern.h>
+
+#define PMU_PWRDN_CON 0x0008
+#define PMU_PWRDN_ST 0x000c
+
+#define SRAM_ENTRY_PA 0x0008
+#define SRAM_DOORBELL 0x0004
+#define SRAM_DOORBELL_MAGIC 0xdeadbeaf
+
+extern struct bus_space arm_generic_bs_tag;
+
+static uint32_t
+rk3066_mpstart_pa(void)
+{
+ bool ok __diagused;
+ paddr_t pa;
+
+ ok = pmap_extract(pmap_kernel(), (vaddr_t)cpu_mpstart, &pa);
+ KASSERT(ok);
+
+ return (uint32_t)pa;
+}
+
+static int
+rk3066_map(int phandle, bus_space_tag_t bst, bus_space_handle_t *pbsh,
+ bus_size_t *psize)
+{
+ bus_addr_t addr;
+ int error;
+
+ error = fdtbus_get_reg(phandle, 0, &addr, psize);
+ if (error != 0) {
+ return error;
+ }
+
+ return bus_space_map(bst, addr, *psize, 0, pbsh);
+}
+
+static int
+rk3066_smp_enable(int cpus_phandle, u_int cpuno)
+{
+ bus_space_tag_t bst = &arm_generic_bs_tag;
+ bus_space_handle_t bsh_sram, bsh_pmu;
+ bus_size_t sz_sram, sz_pmu;
+ uint32_t val;
+ int error;
+
+ const int sram_phandle =
+ of_find_bycompat(OF_peer(0), "rockchip,rk3066-smp-sram");
+ if (sram_phandle == -1) {
+ printf("%s: missing rockchip,rk3066-smp-sram node\n",
+ __func__);
+ return ENXIO;
+ }
+
+ const int pmu_phandle = fdtbus_get_phandle(cpus_phandle,
+ "rockchip,pmu");
+ if (pmu_phandle == -1) {
+ printf("%s: missing rockchip,pmu xref\n", __func__);
+ return ENXIO;
+ }
+
+ error = rk3066_map(sram_phandle, bst, &bsh_sram, &sz_sram);
+ if (error != 0) {
+ return error;
+ }
+
+ error = rk3066_map(pmu_phandle, bst, &bsh_pmu, &sz_pmu);
+ if (error != 0) {
+ bus_space_unmap(bst, bsh_pmu, sz_pmu);
+ return error;
+ }
+
+ /* Enable the A17 core's power domain */
+ val = bus_space_read_4(bst, bsh_pmu, PMU_PWRDN_CON);
+ val &= ~__BIT(cpuno);
+ bus_space_write_4(bst, bsh_pmu, PMU_PWRDN_CON, val);
+
+ /* Wait for the A17 core to power on */
+ do {
+ val = bus_space_read_4(bst, bsh_pmu, PMU_PWRDN_ST);
+ } while ((val & __BIT(cpuno)) != 0);
+
+ delay(2000);
+
+ /* Set wake vector */
+ bus_space_write_4(bst, bsh_sram, SRAM_ENTRY_PA, rk3066_mpstart_pa());
+ /* Notify boot rom that we are ready to start */
+ bus_space_write_4(bst, bsh_sram, SRAM_DOORBELL, SRAM_DOORBELL_MAGIC);
+ dsb();
+ sev();
+
+ bus_space_unmap(bst, bsh_pmu, sz_pmu);
+ bus_space_unmap(bst, bsh_sram, sz_sram);
+
+ return 0;
+}
+
+static int
+cpu_enable_rk3066(int phandle)
+{
+ static uint32_t enabled;
+ uint64_t mpidr;
+ int error = 0;
+
+ fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
+
+ const u_int cpuno = __SHIFTOUT(mpidr, MPIDR_AFF0);
+ const bool is_enabled = enabled & __BIT(cpuno);
+
+ if (!is_enabled) {
+ error = rk3066_smp_enable(OF_parent(phandle), cpuno);
+ if (error == 0) {
+ enabled |= __BIT(cpuno);
+ }
+ } else {
+ printf("WARNING: CPU enable called more than once for CPU %u\n",
+ cpuno);
+ }
+
+ return error;
+}
+
+ARM_CPU_METHOD(rk3066, "rockchip,rk3066-smp", cpu_enable_rk3066);
diff -r 03f45eccd1cc -r 9dd7fe02b248 sys/arch/arm/rockchip/rk3288_cru.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/rockchip/rk3288_cru.c Fri Nov 12 22:02:08 2021 +0000
@@ -0,0 +1,309 @@
+/* $NetBSD: rk3288_cru.c,v 1.1 2021/11/12 22:02:08 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2021 Jared McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+
+__KERNEL_RCSID(1, "$NetBSD: rk3288_cru.c,v 1.1 2021/11/12 22:02:08 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/rockchip/rk_cru.h>
+#include <arm/rockchip/rk3288_cru.h>
+
+#define PLL_CON(n) (0x0000 + (n) * 4)
+#define MODE_CON 0x0050
+#define CLKSEL_CON(n) (0x0060 + (n) * 4)
+#define CLKGATE_CON(n) (0x0160 + (n) * 4)
+#define SOFTRST_CON(n) (0x01b8 + (n) * 4)
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