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[src/netbsd-9]: src/sys/dev/pci Pull up the following revisions, requested by...
details: https://anonhg.NetBSD.org/src/rev/3238b2f25326
branches: netbsd-9
changeset: 1026624:3238b2f25326
user: martin <martin%NetBSD.org@localhost>
date: Fri Dec 03 19:40:38 2021 +0000
description:
Pull up the following revisions, requested by msaitoh in ticket #1384:
sys/dev/pci/pcireg.h 1.152-1.154, 1.156-1.161
sys/dev/pci/pci_subr.c 1.222, 1.227-1.232 via patch
sys/dev/pci/nvme_pci.c 1.31
sys/dev/pci/pci.c 1.158, 1.163
sys/dev/pci/ppb.c 1.74
- When parsing Enhanced Allocation entries, use the correct calculation
for finding the next entry.
- Add 32.0GT/s to the list of pcie speeds (PCIe 5.x.).
- Add Some PCI config information:
- Lane Margining at the Receiver
- NVME admin interface
- UFSHCI
- InfiniBand
- Host fabric
- HDA 1.0 with vendor ext
- USB4 HCI
- MIPI I3C
- Cellular controller/modem (+ Ethernet)
- Change PCI_VENDOR_MASK and PCI_PRODUCT_MASK to unsigned values, to
prevent sign extension of product ID when shifted up into place in
PCI_ID_CODE(). Fixes PR kern/56176.
- Add LCAP & LCAP2 definitions.
- Use PCI-SIG official acronyms for some macros.
- Fix typo in some messages.
- Fix typo in comments.
- Whitespace fixes.
diffstat:
sys/dev/pci/nvme_pci.c | 6 +-
sys/dev/pci/pci.c | 8 +-
sys/dev/pci/pci_subr.c | 73 ++++++++++++++++++---------
sys/dev/pci/pcireg.h | 130 ++++++++++++++++++++++++++++--------------------
sys/dev/pci/ppb.c | 8 +-
5 files changed, 136 insertions(+), 89 deletions(-)
diffs (truncated from 650 to 300 lines):
diff -r d976523d9a3b -r 3238b2f25326 sys/dev/pci/nvme_pci.c
--- a/sys/dev/pci/nvme_pci.c Fri Dec 03 18:20:40 2021 +0000
+++ b/sys/dev/pci/nvme_pci.c Fri Dec 03 19:40:38 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: nvme_pci.c,v 1.26.4.1 2021/06/21 17:25:48 martin Exp $ */
+/* $NetBSD: nvme_pci.c,v 1.26.4.2 2021/12/03 19:40:38 martin Exp $ */
/* $OpenBSD: nvme_pci.c,v 1.3 2016/04/14 11:18:32 dlg Exp $ */
/*
@@ -43,7 +43,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: nvme_pci.c,v 1.26.4.1 2021/06/21 17:25:48 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: nvme_pci.c,v 1.26.4.2 2021/12/03 19:40:38 martin Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -135,7 +135,7 @@
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_NVM &&
- PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_NVM_NVME)
+ PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_NVM_NVME_IO)
return 1;
return 0;
diff -r d976523d9a3b -r 3238b2f25326 sys/dev/pci/pci.c
--- a/sys/dev/pci/pci.c Fri Dec 03 18:20:40 2021 +0000
+++ b/sys/dev/pci/pci.c Fri Dec 03 19:40:38 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci.c,v 1.154.4.2 2019/11/06 09:52:20 martin Exp $ */
+/* $NetBSD: pci.c,v 1.154.4.3 2021/12/03 19:40:38 martin Exp $ */
/*
* Copyright (c) 1995, 1996, 1997, 1998
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.154.4.2 2019/11/06 09:52:20 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci.c,v 1.154.4.3 2021/12/03 19:40:38 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -708,7 +708,7 @@
if (pci_get_capability(ppbpc, ppbtag, PCI_CAP_PCIEXPRESS,
&pciecap, &capreg) != 0) {
switch (PCIE_XCAP_TYPE(capreg)) {
- case PCIE_XCAP_TYPE_ROOT:
+ case PCIE_XCAP_TYPE_RP:
case PCIE_XCAP_TYPE_DOWN:
case PCIE_XCAP_TYPE_PCI2PCIE:
downstream_port = true;
@@ -934,7 +934,7 @@
/* For MSI */
if (pci_get_capability(pc, tag, PCI_CAP_MSI, &off, NULL) != 0) {
bool bit64, pvmask;
-
+
pcs->msi_ctl = pci_conf_read(pc, tag, off + PCI_MSI_CTL);
bit64 = pcs->msi_ctl & PCI_MSI_CTL_64BIT_ADDR;
diff -r d976523d9a3b -r 3238b2f25326 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c Fri Dec 03 18:20:40 2021 +0000
+++ b/sys/dev/pci/pci_subr.c Fri Dec 03 19:40:38 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.215.2.4 2020/07/26 10:46:14 martin Exp $ */
+/* $NetBSD: pci_subr.c,v 1.215.2.5 2021/12/03 19:40:38 martin Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.215.2.4 2020/07/26 10:46:14 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.215.2.5 2021/12/03 19:40:38 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -129,7 +129,15 @@
static const struct pci_class pci_interface_nvm[] = {
{ "vendor specific", PCI_INTERFACE_NVM_VND, NULL, },
{ "NVMHCI 1.0", PCI_INTERFACE_NVM_NVMHCI10, NULL, },
- { "NVMe", PCI_INTERFACE_NVM_NVME, NULL, },
+ { "NVMe I/O", PCI_INTERFACE_NVM_NVME_IO, NULL, },
+ { "NVMe admin", PCI_INTERFACE_NVM_NVME_ADMIN, NULL, },
+ { NULL, 0, NULL, },
+};
+
+/* UFS programming interface */
+static const struct pci_class pci_interface_ufs[] = {
+ { "vendor specific", PCI_INTERFACE_UFS_VND, NULL, },
+ { "UFSHCI", PCI_INTERFACE_UFS_UFSHCI, NULL, },
{ NULL, 0, NULL, },
};
@@ -147,6 +155,8 @@
{ "SAS", PCI_SUBCLASS_MASS_STORAGE_SAS, NULL, },
{ "Flash", PCI_SUBCLASS_MASS_STORAGE_NVM,
pci_interface_nvm, },
+ { "UFS", PCI_SUBCLASS_MASS_STORAGE_UFS,
+ pci_interface_ufs, },
{ "miscellaneous", PCI_SUBCLASS_MASS_STORAGE_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -163,6 +173,8 @@
{ "ISDN", PCI_SUBCLASS_NETWORK_ISDN, NULL, },
{ "WorldFip", PCI_SUBCLASS_NETWORK_WORLDFIP, NULL, },
{ "PCMIG Multi Computing", PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP, NULL, },
+ { "InfiniBand", PCI_SUBCLASS_NETWORK_INFINIBAND, NULL, },
+ { "Host fabric", PCI_SUBCLASS_NETWORK_HFC, NULL, },
{ "miscellaneous", PCI_SUBCLASS_NETWORK_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -191,11 +203,20 @@
* Class 0x04.
* Multimedia device.
*/
+
+/* HD Audio programming interface */
+static const struct pci_class pci_interface_hda[] = {
+ { "HD Audio 1.0", PCI_INTERFACE_HDAUDIO, NULL, },
+ { "HD Audio 1.0 + vendor ext", PCI_INTERFACE_HDAUDIO_VND, NULL, },
+ { NULL, 0, NULL, },
+};
+
static const struct pci_class pci_subclass_multimedia[] = {
{ "video", PCI_SUBCLASS_MULTIMEDIA_VIDEO, NULL, },
{ "audio", PCI_SUBCLASS_MULTIMEDIA_AUDIO, NULL, },
{ "telephony", PCI_SUBCLASS_MULTIMEDIA_TELEPHONY, NULL,},
- { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO, NULL, },
+ { "mixed mode", PCI_SUBCLASS_MULTIMEDIA_HDAUDIO,
+ pci_interface_hda, },
{ "miscellaneous", PCI_SUBCLASS_MULTIMEDIA_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -431,6 +452,7 @@
{ "OHCI", PCI_INTERFACE_USB_OHCI, NULL, },
{ "EHCI", PCI_INTERFACE_USB_EHCI, NULL, },
{ "xHCI", PCI_INTERFACE_USB_XHCI, NULL, },
+ { "USB4 HCI", PCI_INTERFACE_USB_USB4HCI, NULL, },
{ "other HC", PCI_INTERFACE_USB_OTHERHC, NULL, },
{ "device", PCI_INTERFACE_USB_DEVICE, NULL, },
{ NULL, 0, NULL, },
@@ -460,6 +482,7 @@
pci_interface_ipmi, },
{ "SERCOS", PCI_SUBCLASS_SERIALBUS_SERCOS, NULL, },
{ "CANbus", PCI_SUBCLASS_SERIALBUS_CANBUS, NULL, },
+ { "MIPI I3C", PCI_SUBCLASS_SERIALBUS_MIPI_I3C, NULL, },
{ "miscellaneous", PCI_SUBCLASS_SERIALBUS_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -476,6 +499,8 @@
{ "broadband", PCI_SUBCLASS_WIRELESS_BROADBAND, NULL, },
{ "802.11a (5 GHz)", PCI_SUBCLASS_WIRELESS_802_11A, NULL, },
{ "802.11b (2.4 GHz)", PCI_SUBCLASS_WIRELESS_802_11B, NULL, },
+ { "Cellular", PCI_SUBCLASS_WIRELESS_CELL, NULL, },
+ { "Cellular + Ethernet", PCI_SUBCLASS_WIRELESS_CELL_E, NULL, },
{ "miscellaneous", PCI_SUBCLASS_WIRELESS_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -843,7 +868,7 @@
if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
reg = regs[o2i(pcie_capoff + PCIE_XCAP)];
- if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_ROOT_EVNTC)
+ if (PCIE_XCAP_TYPE(reg) == PCIE_XCAP_TYPE_RC_EVNTC)
subclass = PCI_SUBCLASS_SYSTEM_RCEC;
}
}
@@ -1697,7 +1722,9 @@
}
}
-static const char * const pcie_linkspeeds[] = {"2.5", "5.0", "8.0", "16.0"};
+static const char * const pcie_linkspeeds[] = {
+ "2.5", "5.0", "8.0", "16.0", "32.0"
+};
/*
* Print link speed. This function is used for the following register bits:
@@ -1788,7 +1815,7 @@
printf("Legacy PCI Express Endpoint device\n");
check_upstreamport = true;
break;
- case PCIE_XCAP_TYPE_ROOT: /* 0x4 */
+ case PCIE_XCAP_TYPE_RP: /* 0x4 */
printf("Root Port of PCI Express Root Complex\n");
check_slot = true;
break;
@@ -1809,10 +1836,10 @@
/* Upstream port is not PCIe */
check_slot = true;
break;
- case PCIE_XCAP_TYPE_ROOT_INTEP: /* 0x9 */
+ case PCIE_XCAP_TYPE_RCIEP: /* 0x9 */
printf("Root Complex Integrated Endpoint\n");
break;
- case PCIE_XCAP_TYPE_ROOT_EVNTC: /* 0xa */
+ case PCIE_XCAP_TYPE_RC_EVNTC: /* 0xa */
printf("Root Complex Event Collector\n");
break;
default:
@@ -2575,9 +2602,7 @@
printf(" range: 0x%016" PRIx64 "-0x%016" PRIx64
"\n", base, base + offset);
- entoff += 4;
- entoff += baseis64 ? 8 : 4;
- entoff += offsetis64 ? 8 : 4;
+ entoff += 4 + (4 * entry_size);
}
}
@@ -2692,7 +2717,7 @@
/*
* The type was found. Search capability list again and
- * print all capabilities that the capabiliy type is
+ * print all capabilities that the capability type is
* the same. This is required because some capabilities
* appear multiple times (e.g. HyperTransport capability).
*/
@@ -2859,8 +2884,8 @@
extcapoff + PCI_AER_ROOTERR_CMD);
switch (pcie_devtype) {
- case PCIE_XCAP_TYPE_ROOT: /* Root Port of PCI Express Root Complex */
- case PCIE_XCAP_TYPE_ROOT_EVNTC: /* Root Complex Event Collector */
+ case PCIE_XCAP_TYPE_RP: /* Root Port of PCI Express Root Complex */
+ case PCIE_XCAP_TYPE_RC_EVNTC: /* Root Complex Event Collector */
reg = regs[o2i(extcapoff + PCI_AER_ROOTERR_CMD)];
printf(" Root Error Command register: 0x%08x\n", reg);
pci_conf_print_aer_cap_rooterr_cmd(reg);
@@ -3496,7 +3521,7 @@
/* Endpoint Only */
n = __SHIFTOUT(reg, PCI_MCAST_CAP_WINSIZEREQ);
if (n > 0)
- printf(" Windw Size Requested: %d\n", 1 << (n - 1));
+ printf(" Window Size Requested: %d\n", 1 << (n - 1));
onoff("ECRC Regeneration Supported", reg, PCI_MCAST_CAP_ECRCREGEN);
@@ -3680,7 +3705,7 @@
(unsigned int)__SHIFTOUT(reg, PCI_DPA_CAP_XLCY1));
reg = regs[o2i(extcapoff + PCI_DPA_LATIND)];
- printf(" Latency Indicatior register: 0x%08x\n", reg);
+ printf(" Latency Indicator register: 0x%08x\n", reg);
reg = regs[o2i(extcapoff + PCI_DPA_CS)];
printf(" Status register: 0x%04x\n", reg & 0xffff);
@@ -3726,7 +3751,7 @@
onoff("No ST Mode Supported", reg, PCI_TPH_REQ_CAP_NOST);
onoff("Interrupt Vector Mode Supported", reg, PCI_TPH_REQ_CAP_INTVEC);
onoff("Device Specific Mode Supported", reg, PCI_TPH_REQ_CAP_DEVSPEC);
- onoff("Extend TPH Reqester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ);
+ onoff("Extend TPH Requester Supported", reg, PCI_TPH_REQ_CAP_XTPHREQ);
sttbloc = __SHIFTOUT(reg, PCI_TPH_REQ_CAP_STTBLLOC);
printf(" ST Table Location: %s\n",
pci_conf_print_tph_req_cap_sttabloc(sttbloc));
@@ -4079,7 +4104,7 @@
if (pci_conf_find_cap(regs, PCI_CAP_PCIEXPRESS, &pcie_capoff)) {
uint32_t t = regs[o2i(pcie_capoff)];
- if ((t == PCIE_XCAP_TYPE_ROOT) || (t == PCIE_XCAP_TYPE_DOWN))
+ if ((t == PCIE_XCAP_TYPE_RP) || (t == PCIE_XCAP_TYPE_DOWN))
onoff("Link Activation Supported", reg,
PCI_L1PM_CAP_LA);
}
@@ -4132,7 +4157,7 @@
pcireg_t reg;
uint32_t val;
- printf("\n Precision Time Management\n");
+ printf("\n Precision Time Measurement\n");
reg = regs[o2i(extcapoff + PCI_PTM_CAP)];
printf(" PTM Capability register: 0x%08x\n", reg);
@@ -4269,7 +4294,7 @@
pci_conf_print_dpc_cap },
{ PCI_EXTCAP_L1PM, "L1 PM Substates",
pci_conf_print_l1pm_cap },
- { PCI_EXTCAP_PTM, "Precision Time Management",
+ { PCI_EXTCAP_PTM, "Precision Time Measurement",
pci_conf_print_ptm_cap },
{ PCI_EXTCAP_MPCIE, "M-PCIe",
NULL },
@@ -4281,9 +4306,9 @@
NULL },
{ PCI_EXTCAP_VF_RESIZBAR, "VF Resizable BARs",
NULL },
- { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap },
+ { PCI_EXTCAP_DLF, "Data link Feature", pci_conf_print_dlf_cap },
{ PCI_EXTCAP_PYSLAY_16GT, "Physical Layer 16.0 GT/s", NULL },
- { 0x27, "unknown", NULL },
+ { PCI_EXTCAP_LMR, "Lane Margining at the Receiver", NULL },
{ PCI_EXTCAP_HIERARCHYID, "Hierarchy ID",
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